1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3declare i1 @llvm.amdgcn.class.f32(float, i32)
4
5; Produces error after adding an implicit def to v_cndmask_b32
6
7; GCN-LABEL: {{^}}vcc_shrink_vcc_def:
8; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}}
9; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
10define amdgpu_kernel void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) {
11bb0:
12  %tmp = icmp sgt i32 %arg1, 4
13  %c = icmp eq i32 %arg3, 0
14  %tmp4 = select i1 %c, float %arg, float 1.000000e+00
15  %tmp5 = fcmp ogt float %arg2, 0.000000e+00
16  %tmp6 = fcmp olt float %arg2, 1.000000e+00
17  %tmp7 = fcmp olt float %arg, %tmp4
18  %tmp8 = and i1 %tmp5, %tmp6
19  %tmp9 = and i1 %tmp8, %tmp7
20  br i1 %tmp9, label %bb1, label %bb2
21
22bb1:
23  store volatile i32 0, i32 addrspace(1)* undef
24  br label %bb2
25
26bb2:
27  ret void
28}
29
30; The undef flag on the condition src must be preserved on the
31; implicit vcc use to avoid verifier errors.
32
33; GCN-LABEL: {{^}}preserve_condition_undef_flag:
34; GCN-NOT: vcc
35define amdgpu_kernel void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) {
36bb0:
37  %tmp = icmp sgt i32 %arg1, 4
38  %undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef)
39  %tmp4 = select i1 %undef, float %arg, float 1.000000e+00
40  %tmp5 = fcmp ogt float %arg2, 0.000000e+00
41  %tmp6 = fcmp olt float %arg2, 1.000000e+00
42  %tmp7 = fcmp olt float %arg, undef
43  %tmp8 = and i1 %tmp5, %tmp6
44  %tmp9 = and i1 %tmp8, %tmp7
45  br i1 %tmp9, label %bb1, label %bb2
46
47bb1:
48  store volatile i32 0, i32 addrspace(1)* undef
49  br label %bb2
50
51bb2:
52  ret void
53}
54