1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s
3
4--- |
5  define amdgpu_kernel void @call_no_explicit_exec_dependency () {
6    unreachable
7  }
8
9  declare void @func()
10
11...
12
13# Call should be assumed to read exec
14---
15name: call_no_explicit_exec_dependency
16tracksRegLiveness: true
17liveins:
18  - { reg: '$vgpr0', virtual-reg: '%0' }
19  - { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
20machineFunctionInfo:
21  isEntryFunction: true
22body:             |
23  ; GCN-LABEL: name: call_no_explicit_exec_dependency
24  ; GCN: bb.0:
25  ; GCN:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
26  ; GCN:   liveins: $vgpr0, $sgpr0_sgpr1
27  ; GCN:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
28  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
29  ; GCN:   [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
30  ; GCN:   [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
31  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
32  ; GCN:   $exec = S_MOV_B64_term [[S_AND_B64_]]
33  ; GCN:   SI_MASK_BRANCH %bb.4, implicit $exec
34  ; GCN:   S_BRANCH %bb.1
35  ; GCN: bb.1:
36  ; GCN:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
37  ; GCN:   undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
38  ; GCN:   undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
39  ; GCN:   %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
40  ; GCN:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
41  ; GCN:   undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_CO_U32_e64 %5.sub0, %6.sub0, 0, implicit $exec
42  ; GCN:   %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
43  ; GCN:   %5.sub3:sgpr_128 = S_MOV_B32 61440
44  ; GCN:   %5.sub2:sgpr_128 = S_MOV_B32 0
45  ; GCN:   BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
46  ; GCN:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
47  ; GCN:   [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
48  ; GCN:   [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
49  ; GCN:   $exec = S_MOV_B64_term [[S_AND_B64_1]]
50  ; GCN:   SI_MASK_BRANCH %bb.3, implicit $exec
51  ; GCN:   S_BRANCH %bb.2
52  ; GCN: bb.2:
53  ; GCN:   successors: %bb.3(0x80000000)
54  ; GCN:   %5.sub0:sgpr_128 = COPY %5.sub2
55  ; GCN:   %5.sub1:sgpr_128 = COPY %5.sub2
56  ; GCN:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
57  ; GCN:   BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
58  ; GCN: bb.3:
59  ; GCN:   successors: %bb.4(0x80000000)
60  ; GCN:   $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
61  ; GCN:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
62  ; GCN:   dead %16:sreg_64 = SI_CALL [[DEF]], @func, csr_amdgpu_highregs
63  ; GCN: bb.4:
64  ; GCN:   $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
65  ; GCN:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
66  ; GCN:   [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
67  ; GCN:   $m0 = S_MOV_B32 -1
68  ; GCN:   DS_WRITE_B32 [[V_MOV_B32_e32_2]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
69  ; GCN:   S_ENDPGM 0
70  bb.0:
71    successors: %bb.1, %bb.4
72    liveins: $vgpr0, $sgpr0_sgpr1
73
74    %1:sgpr_64 = COPY $sgpr0_sgpr1
75    %0:vgpr_32 = COPY $vgpr0
76    %2:sreg_64 = V_CMP_LT_U32_e64 1, %0, implicit $exec
77    %3:sreg_64 = COPY $exec, implicit-def $exec
78    %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
79    $exec = S_MOV_B64_term %4
80    SI_MASK_BRANCH %bb.4, implicit $exec
81    S_BRANCH %bb.1
82
83  bb.1:
84    successors: %bb.2, %bb.3
85
86    undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
87    undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
88    %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
89    %7:vgpr_32 = COPY %5.sub1
90    undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_CO_U32_e64 %5.sub0, %6.sub0, 0, implicit $exec
91    %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
92    %5.sub3:sgpr_128 = S_MOV_B32 61440
93    %5.sub2:sgpr_128 = S_MOV_B32 0
94    BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
95    %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
96    %12:sreg_64 = COPY $exec, implicit-def $exec
97    %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
98    $exec = S_MOV_B64_term %13
99    SI_MASK_BRANCH %bb.3, implicit $exec
100    S_BRANCH %bb.2
101
102  bb.2:
103    %5.sub0:sgpr_128 = COPY %5.sub2
104    %5.sub1:sgpr_128 = COPY %5.sub2
105    %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
106    BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
107
108  bb.3:
109    $exec = S_OR_B64 $exec, %12,  implicit-def $scc
110    %20:sreg_64 = IMPLICIT_DEF
111    %21:sreg_64 = SI_CALL %20, @func, csr_amdgpu_highregs
112
113  bb.4:
114    $exec = S_OR_B64 $exec, %3, implicit-def $scc
115    %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
116    %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
117    $m0 = S_MOV_B32 -1
118    DS_WRITE_B32 %18, %17, 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
119    S_ENDPGM 0
120
121...
122