1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s 3; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone 6 7declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 8declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone 9declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone 10 11declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 12declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone 13declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone 14 15declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 16 17; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32: 18; GCN: s_load_dword [[VAL:s[0-9]+]], 19; GCN: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] 20; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] 21; GCN: buffer_store_dword [[VRESULT]], 22; GCN: s_endpgm 23; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 24; EG: FFBH_UINT {{\*? *}}[[RESULT]] 25define amdgpu_kernel void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { 26 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 27 store i32 %ctlz, i32 addrspace(1)* %out, align 4 28 ret void 29} 30 31; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32: 32; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 33; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 34; GCN: buffer_store_dword [[RESULT]], 35; GCN: s_endpgm 36; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 37; EG: FFBH_UINT {{\*? *}}[[RESULT]] 38define amdgpu_kernel void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 39 %tid = call i32 @llvm.amdgcn.workitem.id.x() 40 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 41 %val = load i32, i32 addrspace(1)* %in.gep, align 4 42 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 43 store i32 %ctlz, i32 addrspace(1)* %out, align 4 44 ret void 45} 46 47; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32: 48; GCN: {{buffer|flat}}_load_dwordx2 49; GCN: v_ffbh_u32_e32 50; GCN: v_ffbh_u32_e32 51; GCN: buffer_store_dwordx2 52; GCN: s_endpgm 53; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 54; EG: FFBH_UINT {{\*? *}}[[RESULT]] 55; EG: FFBH_UINT {{\*? *}}[[RESULT]] 56define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind { 57 %tid = call i32 @llvm.amdgcn.workitem.id.x() 58 %in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid 59 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8 60 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone 61 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8 62 ret void 63} 64 65; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32: 66; GCN: {{buffer|flat}}_load_dwordx4 67; GCN: v_ffbh_u32_e32 68; GCN: v_ffbh_u32_e32 69; GCN: v_ffbh_u32_e32 70; GCN: v_ffbh_u32_e32 71; GCN: buffer_store_dwordx4 72; GCN: s_endpgm 73; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 74; EG: FFBH_UINT {{\*? *}}[[RESULT]] 75; EG: FFBH_UINT {{\*? *}}[[RESULT]] 76; EG: FFBH_UINT {{\*? *}}[[RESULT]] 77; EG: FFBH_UINT {{\*? *}}[[RESULT]] 78define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind { 79 %tid = call i32 @llvm.amdgcn.workitem.id.x() 80 %in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid 81 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16 82 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone 83 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16 84 ret void 85} 86 87; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8: 88; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 89; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 90; GCN: buffer_store_byte [[RESULT]], 91define amdgpu_kernel void @v_ctlz_zero_undef_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 92 %tid = call i32 @llvm.amdgcn.workitem.id.x() 93 %in.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 94 %val = load i8, i8 addrspace(1)* %in.gep 95 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 96 store i8 %ctlz, i8 addrspace(1)* %out 97 ret void 98} 99 100; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64: 101; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} 102; SI-DAG: v_cmp_eq_u32_e64 vcc, s[[HI]], 0{{$}} 103; VI-DAG: s_cmp_eq_u32 s[[HI]], 0{{$}} 104; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]] 105; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32 106; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]] 107; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[ADD]] 108; SI-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]] 109; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]] 110; VI-DAG: s_cselect_b32 [[RES:s[0-9]+]], [[ADD]], [[FFBH_HI]] 111; GCN-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} 112; VI-DAG: v_mov_b32_e32 v[[CTLZ:[0-9]+]], [[RES]] 113; GCN: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} 114define amdgpu_kernel void @s_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind { 115 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 116 store i64 %ctlz, i64 addrspace(1)* %out 117 ret void 118} 119 120; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64_trunc: 121define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind { 122 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 123 %trunc = trunc i64 %ctlz to i32 124 store i32 %trunc, i32 addrspace(1)* %out 125 ret void 126} 127 128; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64: 129; GCN-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} 130; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, v[[HI]] 131; GCN-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]] 132; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] 133; GCN-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]] 134; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]] 135; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI:[0-9]+]]{{\]}} 136define amdgpu_kernel void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 137 %tid = call i32 @llvm.amdgcn.workitem.id.x() 138 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 139 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 140 %val = load i64, i64 addrspace(1)* %in.gep 141 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 142 store i64 %ctlz, i64 addrspace(1)* %out.gep 143 ret void 144} 145 146; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64_trunc: 147define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 148 %tid = call i32 @llvm.amdgcn.workitem.id.x() 149 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 150 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 151 %val = load i64, i64 addrspace(1)* %in.gep 152 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 153 %trunc = trunc i64 %ctlz to i32 154 store i32 %trunc, i32 addrspace(1)* %out.gep 155 ret void 156} 157 158; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1: 159; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 160; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 161; GCN: buffer_store_dword [[RESULT]], 162define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 163 %tid = call i32 @llvm.amdgcn.workitem.id.x() 164 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 165 %val = load i32, i32 addrspace(1)* %in.gep 166 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 167 %cmp = icmp eq i32 %val, 0 168 %sel = select i1 %cmp, i32 -1, i32 %ctlz 169 store i32 %sel, i32 addrspace(1)* %out 170 ret void 171} 172 173; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_neg1: 174; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 175; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 176; GCN: buffer_store_dword [[RESULT]], 177define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 178 %tid = call i32 @llvm.amdgcn.workitem.id.x() 179 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 180 %val = load i32, i32 addrspace(1)* %in.gep 181 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 182 %cmp = icmp ne i32 %val, 0 183 %sel = select i1 %cmp, i32 %ctlz, i32 -1 184 store i32 %sel, i32 addrspace(1)* %out 185 ret void 186} 187 188; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8_sel_eq_neg1: 189; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 190; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]] 191; GCN: {{buffer|flat}}_store_byte [[FFBH]], 192define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 193 %tid = call i32 @llvm.amdgcn.workitem.id.x() 194 %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 195 %val = load i8, i8 addrspace(1)* %valptr.gep 196 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 197 %cmp = icmp eq i8 %val, 0 198 %sel = select i1 %cmp, i8 -1, i8 %ctlz 199 store i8 %sel, i8 addrspace(1)* %out 200 ret void 201} 202 203; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1_two_use: 204; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 205; GCN-DAG: v_ffbh_u32_e32 [[RESULT0:v[0-9]+]], [[VAL]] 206; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, [[VAL]] 207; GCN-DAG: v_cndmask_b32_e64 [[RESULT1:v[0-9]+]], 0, 1, vcc 208; GCN-DAG: buffer_store_dword [[RESULT0]] 209; GCN-DAG: buffer_store_byte [[RESULT1]] 210; GCN: s_endpgm 211define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 212 %tid = call i32 @llvm.amdgcn.workitem.id.x() 213 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 214 %val = load i32, i32 addrspace(1)* %in.gep 215 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 216 %cmp = icmp eq i32 %val, 0 217 %sel = select i1 %cmp, i32 -1, i32 %ctlz 218 store volatile i32 %sel, i32 addrspace(1)* %out 219 store volatile i1 %cmp, i1 addrspace(1)* undef 220 ret void 221} 222 223; Selected on wrong constant 224; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_0: 225; GCN: {{buffer|flat}}_load_dword 226; GCN: v_ffbh_u32_e32 227; GCN: v_cmp 228; GCN: v_cndmask 229; GCN: buffer_store_dword 230define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 231 %tid = call i32 @llvm.amdgcn.workitem.id.x() 232 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 233 %val = load i32, i32 addrspace(1)* %in.gep 234 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 235 %cmp = icmp eq i32 %val, 0 236 %sel = select i1 %cmp, i32 0, i32 %ctlz 237 store i32 %sel, i32 addrspace(1)* %out 238 ret void 239} 240 241; Selected on wrong constant 242; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_0: 243; GCN: {{buffer|flat}}_load_dword 244; GCN: v_ffbh_u32_e32 245; GCN: v_cmp 246; GCN: v_cndmask 247; GCN: buffer_store_dword 248define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 249 %tid = call i32 @llvm.amdgcn.workitem.id.x() 250 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 251 %val = load i32, i32 addrspace(1)* %in.gep 252 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 253 %cmp = icmp ne i32 %val, 0 254 %sel = select i1 %cmp, i32 %ctlz, i32 0 255 store i32 %sel, i32 addrspace(1)* %out 256 ret void 257} 258 259; Compare on wrong constant 260; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_cmp_non0: 261; GCN: {{buffer|flat}}_load_dword 262; GCN: v_ffbh_u32_e32 263; GCN: v_cmp 264; GCN: v_cndmask 265; GCN: buffer_store_dword 266define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 267 %tid = call i32 @llvm.amdgcn.workitem.id.x() 268 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 269 %val = load i32, i32 addrspace(1)* %in.gep 270 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 271 %cmp = icmp eq i32 %val, 1 272 %sel = select i1 %cmp, i32 0, i32 %ctlz 273 store i32 %sel, i32 addrspace(1)* %out 274 ret void 275} 276 277; Selected on wrong constant 278; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_cmp_non0: 279; GCN: {{buffer|flat}}_load_dword 280; GCN: v_ffbh_u32_e32 281; GCN: v_cmp 282; GCN: v_cndmask 283; GCN: buffer_store_dword 284define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 285 %tid = call i32 @llvm.amdgcn.workitem.id.x() 286 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 287 %val = load i32, i32 addrspace(1)* %in.gep 288 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 289 %cmp = icmp ne i32 %val, 1 290 %sel = select i1 %cmp, i32 %ctlz, i32 0 291 store i32 %sel, i32 addrspace(1)* %out 292 ret void 293} 294