1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; We are only checking that instruction selection can succeed in this case. This
4; cut down test results in no instructions, but that's fine.
5;
6; See https://llvm.org/PR33743 for details of the bug being addressed
7;
8; Checking that shufflevector with 3-vec mask is handled in
9; combineShuffleToVectorExtend
10;
11; GCN: s_endpgm
12
13define amdgpu_ps void @main(i32 %in1) local_unnamed_addr {
14.entry:
15  br i1 undef, label %bb12, label %bb
16
17bb:
18  %__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> undef, i32 %in1, i32 3
19  %tmp3 = shufflevector <4 x i32> %__llpc_global_proxy_r5.12.vec.insert, <4 x i32> undef, <3 x i32> <i32 undef, i32 undef, i32 1>
20  %tmp4 = bitcast <3 x i32> %tmp3 to <3 x float>
21  %a2.i123 = extractelement <3 x float> %tmp4, i32 2
22  %tmp5 = bitcast float %a2.i123 to i32
23  %__llpc_global_proxy_r2.0.vec.insert196 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
24  br label %bb12
25
26bb12:
27  %__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ undef, %.entry ]
28  %tmp6 = shufflevector <4 x i32> %__llpc_global_proxy_r2.0, <4 x i32> undef, <3 x i32> <i32 1, i32 2, i32 3>
29  %tmp7 = bitcast <3 x i32> %tmp6 to <3 x float>
30  %a0.i = extractelement <3 x float> %tmp7, i32 0
31  ret void
32}
33