1; RUN: llc -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-FMF,GCN-SAFE %s
2
3declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
4
5; Test that the -enable-no-signed-zeros-fp-math flag works
6
7; GCN-LABEL: {{^}}fneg_fsub_f32_fmf:
8; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
9; GCN-FMF-NOT: xor
10define amdgpu_kernel void @fneg_fsub_f32_fmf(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
11  %tid = call i32 @llvm.amdgcn.workitem.id.x()
12  %add = add i32 %tid, 1
13  %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
14  %b_ptr = getelementptr float, float addrspace(1)* %in, i32 %add
15  %a = load float, float addrspace(1)* %gep, align 4
16  %b = load float, float addrspace(1)* %b_ptr, align 4
17  %result = fsub fast float %a, %b
18  %neg.result = fsub fast float -0.0, %result
19  store float %neg.result, float addrspace(1)* %out, align 4
20  ret void
21}
22
23; GCN-LABEL: {{^}}fneg_fsub_f32_safe:
24; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
25; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]
26define amdgpu_kernel void @fneg_fsub_f32_safe(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
27  %tid = call i32 @llvm.amdgcn.workitem.id.x()
28  %add = add i32 %tid, 1
29  %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
30  %b_ptr = getelementptr float, float addrspace(1)* %in, i32 %add
31  %a = load float, float addrspace(1)* %gep, align 4
32  %b = load float, float addrspace(1)* %b_ptr, align 4
33  %result = fsub float %a, %b
34  %neg.result = fsub float -0.0, %result
35  store float %neg.result, float addrspace(1)* %out, align 4
36  ret void
37}
38
39attributes #0 = { nounwind }
40