1# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s 2 3# GCN-LABEL: name: kill_all 4# GCN: bb.0: 5# GCN-NEXT: S_ENDPGM 0 6name: kill_all 7tracksRegLiveness: true 8registers: 9 - { id: 0, class: vreg_64 } 10 - { id: 1, class: vgpr_32 } 11 - { id: 2, class: vgpr_32 } 12 - { id: 3, class: sgpr_32 } 13 - { id: 4, class: sgpr_32 } 14body: | 15 bb.0: 16 $vcc = IMPLICIT_DEF 17 %0 = IMPLICIT_DEF 18 %3 = IMPLICIT_DEF 19 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 20 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) 21 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec 22 %4 = S_ADD_U32 %3, 1, implicit-def $scc 23 S_ENDPGM 0 24... 25--- 26# GCN-LABEL: name: load_without_memoperand 27# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 28# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 29# GCN-NEXT: S_ENDPGM 0 30name: load_without_memoperand 31tracksRegLiveness: true 32registers: 33 - { id: 0, class: vreg_64 } 34 - { id: 1, class: vgpr_32 } 35 - { id: 2, class: vgpr_32 } 36 - { id: 3, class: sgpr_32 } 37 - { id: 4, class: sgpr_32 } 38body: | 39 bb.0: 40 $vcc = IMPLICIT_DEF 41 %0 = IMPLICIT_DEF 42 %3 = IMPLICIT_DEF 43 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 44 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 45 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec 46 %4 = S_ADD_U32 %3, 1, implicit-def $scc 47 S_ENDPGM 0 48... 49--- 50# GCN-LABEL: name: load_volatile 51# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 52# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4) 53# GCN-NEXT: S_ENDPGM 0 54name: load_volatile 55tracksRegLiveness: true 56registers: 57 - { id: 0, class: vreg_64 } 58 - { id: 1, class: vgpr_32 } 59 - { id: 2, class: vgpr_32 } 60 - { id: 3, class: sgpr_32 } 61 - { id: 4, class: sgpr_32 } 62body: | 63 bb.0: 64 $vcc = IMPLICIT_DEF 65 %0 = IMPLICIT_DEF 66 %3 = IMPLICIT_DEF 67 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 68 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4) 69 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec 70 %4 = S_ADD_U32 %3, 1, implicit-def $scc 71 S_ENDPGM 0 72... 73--- 74# GCN-LABEL: name: store 75# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 76# GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) 77# GCN-NEXT: S_ENDPGM 0 78name: store 79tracksRegLiveness: true 80registers: 81 - { id: 0, class: vreg_64 } 82 - { id: 1, class: vgpr_32 } 83body: | 84 bb.0: 85 $vcc = IMPLICIT_DEF 86 %0 = IMPLICIT_DEF 87 %1 = IMPLICIT_DEF 88 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 89 FLAT_STORE_DWORD %0, %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) 90 S_ENDPGM 0 91... 92--- 93# GCN-LABEL: name: barrier 94# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 95# GCN-NEXT: S_BARRIER 96# GCN-NEXT: S_ENDPGM 0 97name: barrier 98tracksRegLiveness: true 99body: | 100 bb.0: 101 $vcc = IMPLICIT_DEF 102 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 103 S_BARRIER 104 S_ENDPGM 0 105... 106--- 107# GCN-LABEL: name: call 108# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 109# GCN-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3 110# GCN-NEXT: S_ENDPGM 0 111name: call 112tracksRegLiveness: true 113body: | 114 bb.0: 115 liveins: $sgpr2_sgpr3 116 $vcc = IMPLICIT_DEF 117 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 118 $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3 119 S_ENDPGM 0 120... 121--- 122# GCN-LABEL: name: exp 123# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 124# GCN-NEXT: EXP 32, undef %0:vgpr_32, undef %1:vgpr_32, %2, undef %3:vgpr_32, 0, 0, 15, implicit $exec 125# GCN-NEXT: S_ENDPGM 0 126name: exp 127tracksRegLiveness: true 128registers: 129 - { id: 0, class: vgpr_32 } 130 - { id: 1, class: vgpr_32 } 131 - { id: 2, class: vgpr_32 } 132 - { id: 3, class: vgpr_32 } 133body: | 134 bb.0: 135 $vcc = IMPLICIT_DEF 136 %2 = IMPLICIT_DEF 137 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 138 EXP 32, undef %0, undef %1, killed %2, undef %3, 0, 0, 15, implicit $exec 139 S_ENDPGM 0 140... 141--- 142# GCN-LABEL: name: return_to_epilog 143# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 144# GCN-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0 145name: return_to_epilog 146tracksRegLiveness: true 147body: | 148 bb.0: 149 $vcc = IMPLICIT_DEF 150 $vgpr0 = IMPLICIT_DEF 151 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 152 SI_RETURN_TO_EPILOG killed $vgpr0 153... 154--- 155# GCN-LABEL: name: split_block 156# GCN: bb.0: 157# GCN-NEXT: successors: %bb.1 158# GCN-NOT: S_OR_B64 159# GCN: bb.1: 160# GCN-NEXT: S_ENDPGM 0 161name: split_block 162tracksRegLiveness: true 163registers: 164 - { id: 0, class: vgpr_32 } 165 - { id: 1, class: vgpr_32 } 166 - { id: 2, class: sgpr_32 } 167 - { id: 3, class: sgpr_32 } 168body: | 169 bb.0: 170 $vcc = IMPLICIT_DEF 171 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 172 173 bb.1: 174 %0 = IMPLICIT_DEF 175 %2 = IMPLICIT_DEF 176 %1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit $mode, implicit $exec 177 %3 = S_ADD_U32 %2, 1, implicit-def $scc 178 S_ENDPGM 0 179... 180--- 181# GCN-LABEL: name: split_block_empty_block 182# GCN: bb.0: 183# GCN-NEXT: successors: %bb.1 184# GCN-NOT: S_OR_B64 185# GCN: bb.1: 186# GCN: bb.2: 187# GCN-NEXT: S_ENDPGM 0 188name: split_block_empty_block 189tracksRegLiveness: true 190body: | 191 bb.0: 192 $vcc = IMPLICIT_DEF 193 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 194 195 bb.1: 196 197 bb.2: 198 S_ENDPGM 0 199... 200--- 201# GCN-LABEL: name: split_block_uncond_branch 202# GCN: bb.0: 203# GCN-NEXT: successors: %bb.1 204# GCN: S_BRANCH %bb.1 205# GCN-NOT: S_OR_B64 206# GCN: bb.1: 207# GCN-NEXT: S_ENDPGM 0 208name: split_block_uncond_branch 209tracksRegLiveness: true 210body: | 211 bb.0: 212 $vcc = IMPLICIT_DEF 213 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 214 S_BRANCH %bb.1 215 216 bb.1: 217 S_ENDPGM 0 218... 219--- 220# GCN-LABEL: name: split_block_cond_branch 221# GCN: bb.0: 222# GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) 223# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc 224# GCN: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc 225# GCN: bb.1: 226# GCN: bb.2: 227# GCN-NEXT: S_ENDPGM 0 228name: split_block_cond_branch 229tracksRegLiveness: true 230body: | 231 bb.0: 232 $vcc = IMPLICIT_DEF 233 $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc 234 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc 235 236 bb.1: 237 238 bb.2: 239 S_ENDPGM 0 240... 241--- 242# GCN-LABEL: name: two_preds_both_dead 243# GCN: bb.0: 244# GCN-NEXT: successors: %bb.2 245# GCN-NOT: S_OR 246# GCN: S_BRANCH %bb.2 247# GCN: bb.1: 248# GCN-NEXT: successors: %bb.2 249# GCN-NOT: S_AND 250# GCN: S_BRANCH %bb.2 251# GCN: bb.2: 252# GCN-NEXT: S_ENDPGM 0 253name: two_preds_both_dead 254tracksRegLiveness: true 255body: | 256 bb.0: 257 $vcc = IMPLICIT_DEF 258 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 259 S_BRANCH %bb.2 260 261 bb.1: 262 $vcc = IMPLICIT_DEF 263 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc 264 S_BRANCH %bb.2 265 266 bb.2: 267 S_ENDPGM 0 268... 269--- 270# GCN-LABEL: name: two_preds_one_dead 271# GCN: bb.0: 272# GCN-NEXT: successors: %bb.2 273# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 274# GCN-NEXT: S_BARRIER 275# GCN-NEXT: S_BRANCH %bb.2 276# GCN: bb.1: 277# GCN-NEXT: successors: %bb.2 278# GCN-NOT: S_AND 279# GCN: S_BRANCH %bb.2 280# GCN: bb.2: 281# GCN-NEXT: S_ENDPGM 0 282name: two_preds_one_dead 283tracksRegLiveness: true 284body: | 285 bb.0: 286 $vcc = IMPLICIT_DEF 287 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 288 S_BARRIER 289 S_BRANCH %bb.2 290 291 bb.1: 292 $vcc = IMPLICIT_DEF 293 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc 294 S_BRANCH %bb.2 295 296 bb.2: 297 S_ENDPGM 0 298... 299 300# GCN-LABEL: name: implicit_use_on_S_ENDPGM 0 301# GCN: V_ADD_CO_U32 302# GCN: COPY 303# GCN: V_ADDC_U32 304# GCN: S_ENDPGM 0, implicit %3 305name: implicit_use_on_S_ENDPGM 0 306tracksRegLiveness: true 307 308body: | 309 bb.0: 310 dead %0:vgpr_32 = V_ADD_CO_U32_e32 12345, undef %1:vgpr_32, implicit-def $vcc, implicit $exec 311 %2:sreg_64_xexec = COPY $vcc 312 %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 undef %5:vgpr_32, undef %6:vgpr_32, %2, 0, implicit $exec 313 S_ENDPGM 0, implicit %3 314 315... 316 317--- 318# GCN-LABEL: name: inlineasm_nosideeffect 319# GCN-NOT: S_OR_B64 320# GCN-NOT: INLINEASM 321# GCN: S_ENDPGM 0 322name: inlineasm_nosideeffect 323tracksRegLiveness: true 324registers: 325 - { id: 0, class: vreg_64 } 326 - { id: 1, class: vgpr_32 } 327body: | 328 bb.0: 329 $vcc = IMPLICIT_DEF 330 %0 = IMPLICIT_DEF 331 %1 = IMPLICIT_DEF 332 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 333 %2:sreg_64 = IMPLICIT_DEF 334 INLINEASM &"", 0 335 S_ENDPGM 0 336... 337 338--- 339# GCN-LABEL: name: inlineasm_sideeffect 340# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 341# GCN-NEXT: IMPLICIT_DEF 342# GCN-NEXT: INLINEASM 343# GCN-NEXT: S_ENDPGM 0 344name: inlineasm_sideeffect 345tracksRegLiveness: true 346registers: 347 - { id: 0, class: vreg_64 } 348 - { id: 1, class: vgpr_32 } 349body: | 350 bb.0: 351 $vcc = IMPLICIT_DEF 352 %0 = IMPLICIT_DEF 353 %1 = IMPLICIT_DEF 354 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 355 %2:sreg_64 = IMPLICIT_DEF 356 INLINEASM &"", 1 357 S_ENDPGM 0 358... 359