1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 4 5 6; DAGCombiner will transform: 7; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF)) 8; unless isFabsFree returns true 9 10; FUNC-LABEL: {{^}}s_fabs_fn_free: 11; R600-NOT: AND 12; R600: |PV.{{[XYZW]}}| 13 14; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff 15; VI: s_bitset0_b32 s{{[0-9]+}}, 31 16define amdgpu_kernel void @s_fabs_fn_free(float addrspace(1)* %out, i32 %in) { 17 %bc= bitcast i32 %in to float 18 %fabs = call float @fabs(float %bc) 19 store float %fabs, float addrspace(1)* %out 20 ret void 21} 22 23; FUNC-LABEL: {{^}}s_fabs_free: 24; R600-NOT: AND 25; R600: |PV.{{[XYZW]}}| 26 27; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff 28; VI: s_bitset0_b32 s{{[0-9]+}}, 31 29define amdgpu_kernel void @s_fabs_free(float addrspace(1)* %out, i32 %in) { 30 %bc= bitcast i32 %in to float 31 %fabs = call float @llvm.fabs.f32(float %bc) 32 store float %fabs, float addrspace(1)* %out 33 ret void 34} 35 36; FUNC-LABEL: {{^}}s_fabs_f32: 37; R600: |{{(PV|T[0-9])\.[XYZW]}}| 38 39; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff 40; VI: s_bitset0_b32 s{{[0-9]+}}, 31 41define amdgpu_kernel void @s_fabs_f32(float addrspace(1)* %out, float %in) { 42 %fabs = call float @llvm.fabs.f32(float %in) 43 store float %fabs, float addrspace(1)* %out 44 ret void 45} 46 47; FUNC-LABEL: {{^}}fabs_v2f32: 48; R600: |{{(PV|T[0-9])\.[XYZW]}}| 49; R600: |{{(PV|T[0-9])\.[XYZW]}}| 50 51; GCN: s_and_b32 52; GCN: s_and_b32 53define amdgpu_kernel void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { 54 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) 55 store <2 x float> %fabs, <2 x float> addrspace(1)* %out 56 ret void 57} 58 59; FUNC-LABEL: {{^}}fabs_v4f32: 60; R600: |{{(PV|T[0-9])\.[XYZW]}}| 61; R600: |{{(PV|T[0-9])\.[XYZW]}}| 62; R600: |{{(PV|T[0-9])\.[XYZW]}}| 63; R600: |{{(PV|T[0-9])\.[XYZW]}}| 64 65; GCN: s_and_b32 66; GCN: s_and_b32 67; GCN: s_and_b32 68; GCN: s_and_b32 69define amdgpu_kernel void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { 70 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) 71 store <4 x float> %fabs, <4 x float> addrspace(1)* %out 72 ret void 73} 74 75; GCN-LABEL: {{^}}fabs_fn_fold: 76; SI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb 77; VI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c 78; GCN-NOT: and 79; GCN: v_mov_b32_e32 [[V_MUL_VI:v[0-9]+]], s[[MUL_VAL]] 80; GCN: v_mul_f32_e64 v{{[0-9]+}}, |s[[ABS_VALUE]]|, [[V_MUL_VI]] 81define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) { 82 %fabs = call float @fabs(float %in0) 83 %fmul = fmul float %fabs, %in1 84 store float %fmul, float addrspace(1)* %out 85 ret void 86} 87 88; FUNC-LABEL: {{^}}fabs_fold: 89; SI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb 90; VI: s_load_dwordx2 s{{\[}}[[ABS_VALUE:[0-9]+]]:[[MUL_VAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c 91; GCN-NOT: and 92; GCN: v_mov_b32_e32 [[V_MUL_VI:v[0-9]+]], s[[MUL_VAL]] 93; GCN: v_mul_f32_e64 v{{[0-9]+}}, |s[[ABS_VALUE]]|, [[V_MUL_VI]] 94define amdgpu_kernel void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) { 95 %fabs = call float @llvm.fabs.f32(float %in0) 96 %fmul = fmul float %fabs, %in1 97 store float %fmul, float addrspace(1)* %out 98 ret void 99} 100 101; Make sure we turn some integer operations back into fabs 102; FUNC-LABEL: {{^}}bitpreserve_fabs_f32: 103; GCN: v_add_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|, 1.0 104define amdgpu_kernel void @bitpreserve_fabs_f32(float addrspace(1)* %out, float %in) { 105 %in.bc = bitcast float %in to i32 106 %int.abs = and i32 %in.bc, 2147483647 107 %bc = bitcast i32 %int.abs to float 108 %fadd = fadd float %bc, 1.0 109 store float %fadd, float addrspace(1)* %out 110 ret void 111} 112 113declare float @fabs(float) readnone 114declare float @llvm.fabs.f32(float) readnone 115declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone 116declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone 117