1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4; GCN-LABEL: {{^}}fadd_f16 5; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]] 6; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]] 7; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 8; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 9; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]] 10; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 11; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]] 12; GCN: buffer_store_short v[[R_F16]] 13; GCN: s_endpgm 14define amdgpu_kernel void @fadd_f16( 15 half addrspace(1)* %r, 16 half addrspace(1)* %a, 17 half addrspace(1)* %b) { 18entry: 19 %a.val = load volatile half, half addrspace(1)* %a 20 %b.val = load volatile half, half addrspace(1)* %b 21 %r.val = fadd half %a.val, %b.val 22 store half %r.val, half addrspace(1)* %r 23 ret void 24} 25 26; GCN-LABEL: {{^}}fadd_f16_imm_a 27; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]] 28; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 29; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 1.0, v[[B_F32]] 30; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 31; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 1.0, v[[B_F16]] 32; GCN: buffer_store_short v[[R_F16]] 33; GCN: s_endpgm 34define amdgpu_kernel void @fadd_f16_imm_a( 35 half addrspace(1)* %r, 36 half addrspace(1)* %b) { 37entry: 38 %b.val = load half, half addrspace(1)* %b 39 %r.val = fadd half 1.0, %b.val 40 store half %r.val, half addrspace(1)* %r 41 ret void 42} 43 44; GCN-LABEL: {{^}}fadd_f16_imm_b 45; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]] 46; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 47; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 2.0, v[[A_F32]] 48; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 49; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 2.0, v[[A_F16]] 50; GCN: buffer_store_short v[[R_F16]] 51; GCN: s_endpgm 52define amdgpu_kernel void @fadd_f16_imm_b( 53 half addrspace(1)* %r, 54 half addrspace(1)* %a) { 55entry: 56 %a.val = load half, half addrspace(1)* %a 57 %r.val = fadd half %a.val, 2.0 58 store half %r.val, half addrspace(1)* %r 59 ret void 60} 61 62; GCN-LABEL: {{^}}fadd_v2f16: 63; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]] 64; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]] 65; VI: flat_load_dword v[[A_V2_F16:[0-9]+]] 66; VI: flat_load_dword v[[B_V2_F16:[0-9]+]] 67 68; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 69; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 70; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] 71; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 72 73; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 74; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] 75; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[B_F32_0]] 76; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]], v[[B_F32_1]] 77; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 78; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 79; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 80; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] 81 82; VI-DAG: v_add_f16_e32 v[[R_F16_LO:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] 83; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 84; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]] 85 86; GCN: buffer_store_dword v[[R_V2_F16]] 87; GCN: s_endpgm 88define amdgpu_kernel void @fadd_v2f16( 89 <2 x half> addrspace(1)* %r, 90 <2 x half> addrspace(1)* %a, 91 <2 x half> addrspace(1)* %b) { 92entry: 93 %tid = call i32 @llvm.amdgcn.workitem.id.x() 94 %gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid 95 %gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid 96 %a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a 97 %b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b 98 %r.val = fadd <2 x half> %a.val, %b.val 99 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 100 ret void 101} 102 103; GCN-LABEL: {{^}}fadd_v2f16_imm_a: 104; GCN-DAG: {{buffer|flat}}_load_dword v[[B_V2_F16:[0-9]+]] 105; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] 106; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 107; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] 108; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 1.0, v[[B_F32_0]] 109; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 110; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 2.0, v[[B_F32_1]] 111; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 112; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 113; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] 114 115; VI-DAG: v_mov_b32_e32 v[[CONST2:[0-9]+]], 0x4000 116; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[B_V2_F16]], v[[CONST2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 117; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]] 118; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] 119 120; GCN: buffer_store_dword v[[R_V2_F16]] 121; GCN: s_endpgm 122define amdgpu_kernel void @fadd_v2f16_imm_a( 123 <2 x half> addrspace(1)* %r, 124 <2 x half> addrspace(1)* %b) { 125entry: 126 %tid = call i32 @llvm.amdgcn.workitem.id.x() 127 %gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid 128 %b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b 129 %r.val = fadd <2 x half> <half 1.0, half 2.0>, %b.val 130 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 131 ret void 132} 133 134; GCN-LABEL: {{^}}fadd_v2f16_imm_b: 135; GCN-DAG: {{buffer|flat}}_load_dword v[[A_V2_F16:[0-9]+]] 136; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 137; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 138; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 139; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 2.0, v[[A_F32_0]] 140; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 141; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 1.0, v[[A_F32_1]] 142; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 143; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 144; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] 145 146; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00 147; VI-DAG: v_add_f16_sdwa v[[R_F16_0:[0-9]+]], v[[A_V2_F16]], v[[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 148; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[A_V2_F16]] 149; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]] 150 151; GCN: buffer_store_dword v[[R_V2_F16]] 152; GCN: s_endpgm 153define amdgpu_kernel void @fadd_v2f16_imm_b( 154 <2 x half> addrspace(1)* %r, 155 <2 x half> addrspace(1)* %a) { 156entry: 157 %tid = call i32 @llvm.amdgcn.workitem.id.x() 158 %gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid 159 %a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a 160 %r.val = fadd <2 x half> %a.val, <half 2.0, half 1.0> 161 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 162 ret void 163} 164 165declare i32 @llvm.amdgcn.workitem.id.x() #1 166 167attributes #0 = { nounwind } 168attributes #1 = { nounwind readnone } 169