1# RUN: llc -march=amdgcn -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
2
3# GCN-LABEL: name: fix-sgpr-copies
4# GCN: V_ADD_CO_U32_e32
5# GCN: V_ADDC_U32_e32
6---
7name: fix-sgpr-copies
8body:               |
9  bb.0:
10    %0:vgpr_32 = IMPLICIT_DEF
11    %1:sreg_32 = IMPLICIT_DEF
12    %2:sreg_32 = IMPLICIT_DEF
13    %3:sreg_32 = IMPLICIT_DEF
14    %4:vgpr_32 = V_CVT_U32_F32_e64 0, %0:vgpr_32, 0, 0, implicit $mode, implicit $exec
15    %5:sreg_32 = COPY %4:vgpr_32
16    %6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc
17    %7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc
18...
19
20# Test to ensure i1 phi copies from scalar registers through another phi won't
21# be promoted into vector ones.
22# GCN-LABEL: name: fix-sgpr-i1-phi-copies
23# GCN: .8:
24# GCN-NOT: vreg_64 = PHI
25---
26name: fix-sgpr-i1-phi-copies
27tracksRegLiveness: true
28body:               |
29  bb.9:
30    S_BRANCH %bb.0
31
32  bb.4:
33    S_CBRANCH_SCC1 %bb.6, implicit undef $scc
34
35  bb.5:
36    %3:vreg_1 = IMPLICIT_DEF
37
38  bb.6:
39    %4:vreg_1 = PHI %2:sreg_64, %bb.4, %3:vreg_1, %bb.5
40
41  bb.7:
42    %5:vreg_1 = PHI %2:sreg_64, %bb.3, %4:vreg_1, %bb.6
43    S_BRANCH %bb.8
44
45  bb.0:
46    S_CBRANCH_SCC1 %bb.2, implicit undef $scc
47
48  bb.1:
49    %0:sreg_64 = S_MOV_B64 0
50    S_BRANCH %bb.3
51
52  bb.2:
53    %1:sreg_64 = S_MOV_B64 -1
54    S_BRANCH %bb.3
55
56  bb.3:
57    %2:sreg_64 = PHI %0:sreg_64, %bb.1, %1:sreg_64, %bb.2
58    S_CBRANCH_SCC1 %bb.7, implicit undef $scc
59    S_BRANCH %bb.4
60
61  bb.8:
62...
63
64# Avoid infinite loop in SIInstrInfo::legalizeGenericOperand when checking for ImpDef.
65# GCN-LABEL: name: legalize-operand-search-each-def-once
66# GCN-NOT: sreg_64 PHI
67---
68name: legalize-operand-search-each-def-once
69tracksRegLiveness: true
70body:               |
71  bb.0:
72    successors: %bb.1, %bb.2
73    liveins: $sgpr0_sgpr1
74
75    %0:sgpr_64 = COPY $sgpr0_sgpr1
76    S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
77    S_BRANCH %bb.1
78
79  bb.1:
80    %1:vreg_64 = IMPLICIT_DEF
81    S_BRANCH %bb.2
82
83  bb.2:
84    %2:sgpr_64 = PHI %0, %bb.0, %1, %bb.1
85    $sgpr0_sgpr1 = COPY %0
86...
87
88# A REG_SEQUENCE that uses registers defined by both a PHI and a COPY could
89# result in an endless search.
90# GCN-LABEL: name: process-phi-search-each-use-once
91# GCN-NOT: sreg_32 PHI
92---
93name: process-phi-search-each-use-once
94tracksRegLiveness: true
95body:               |
96  bb.0:
97    successors: %bb.1, %bb.2
98    liveins: $vgpr3
99
100    %0:vgpr_32 = COPY $vgpr3
101    S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
102    S_BRANCH %bb.1
103
104  bb.1:
105    %1:sgpr_32 = IMPLICIT_DEF
106    S_BRANCH %bb.2
107
108  bb.2:
109    %2:sgpr_32 = PHI %0, %bb.0, %1, %bb.1
110    %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %0, %subreg.sub1
111    $vgpr3 = COPY %3.sub0
112...
113
114# Test to ensure that undef SCC gets properly propagated.
115# GCN-LABEL: name: scc_undef
116# GCN: S_CSELECT_B64 -1, 0, implicit undef $scc
117# GCN: V_CNDMASK
118---
119name: scc_undef
120tracksRegLiveness: true
121
122body:               |
123  bb.0:
124  %1:vgpr_32 = IMPLICIT_DEF
125  %2:sreg_32 = S_MOV_B32 1
126  %3:sreg_32 = COPY %1:vgpr_32
127  %4:sreg_32 = S_CSELECT_B32 killed %2:sreg_32, killed %3:sreg_32, implicit undef $scc
128---
129