1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=WAVE64 --check-prefix=NOTES %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=WAVE64 --check-prefix=NOTES %s
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=WAVE64 --check-prefix=NOTES %s
4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX1010 --check-prefix=WAVE32 --check-prefix=NOTES %s
5
6@var = addrspace(1) global float 0.0
7
8; CHECK: ---
9; CHECK:  amdhsa.kernels:
10
11; CHECK:   - .args:
12; CHECK:     .group_segment_fixed_size: 0
13; CHECK:     .kernarg_segment_align: 8
14; CHECK:     .kernarg_segment_size: 24
15; CHECK:     .max_flat_workgroup_size: 1024
16; CHECK:     .name:           test
17; CHECK:     .private_segment_fixed_size: 0
18; CHECK:     .sgpr_count:     8
19; CHECK:     .symbol:         test.kd
20; CHECK:     .vgpr_count:     {{3|6}}
21; WAVE64:    .wavefront_size: 64
22; WAVE32:    .wavefront_size: 32
23define amdgpu_kernel void @test(
24    half addrspace(1)* %r,
25    half addrspace(1)* %a,
26    half addrspace(1)* %b) {
27entry:
28  %a.val = load half, half addrspace(1)* %a
29  %b.val = load half, half addrspace(1)* %b
30  %r.val = fadd half %a.val, %b.val
31  store half %r.val, half addrspace(1)* %r
32  ret void
33}
34
35; CHECK:   - .args:
36; CHECK:     .max_flat_workgroup_size: 256
37define amdgpu_kernel void @test_max_flat_workgroup_size(
38    half addrspace(1)* %r,
39    half addrspace(1)* %a,
40    half addrspace(1)* %b) #2 {
41entry:
42  %a.val = load half, half addrspace(1)* %a
43  %b.val = load half, half addrspace(1)* %b
44  %r.val = fadd half %a.val, %b.val
45  store half %r.val, half addrspace(1)* %r
46  ret void
47}
48
49; CHECK:   .name:       num_spilled_sgprs
50; GFX700:   .sgpr_spill_count: 38
51; GFX803:   .sgpr_spill_count: 22
52; GFX900:   .sgpr_spill_count: 48
53; GFX1010:  .sgpr_spill_count: 48
54; CHECK:   .symbol:     num_spilled_sgprs.kd
55define amdgpu_kernel void @num_spilled_sgprs(
56    i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, [8 x i32],
57    i32 addrspace(1)* %out2, i32 addrspace(1)* %out3, [8 x i32],
58    i32 addrspace(1)* %out4, i32 addrspace(1)* %out5, [8 x i32],
59    i32 addrspace(1)* %out6, i32 addrspace(1)* %out7, [8 x i32],
60    i32 addrspace(1)* %out8, i32 addrspace(1)* %out9, [8 x i32],
61    i32 addrspace(1)* %outa, i32 addrspace(1)* %outb, [8 x i32],
62    i32 addrspace(1)* %outc, i32 addrspace(1)* %outd, [8 x i32],
63    i32 addrspace(1)* %oute, i32 addrspace(1)* %outf, [8 x i32],
64    i32 %in0, i32 %in1, i32 %in2, i32 %in3, [8 x i32],
65    i32 %in4, i32 %in5, i32 %in6, i32 %in7, [8 x i32],
66    i32 %in8, i32 %in9, i32 %ina, i32 %inb, [8 x i32],
67    i32 %inc, i32 %ind, i32 %ine, i32 %inf) #0 {
68entry:
69  store i32 %in0, i32 addrspace(1)* %out0
70  store i32 %in1, i32 addrspace(1)* %out1
71  store i32 %in2, i32 addrspace(1)* %out2
72  store i32 %in3, i32 addrspace(1)* %out3
73  store i32 %in4, i32 addrspace(1)* %out4
74  store i32 %in5, i32 addrspace(1)* %out5
75  store i32 %in6, i32 addrspace(1)* %out6
76  store i32 %in7, i32 addrspace(1)* %out7
77  store i32 %in8, i32 addrspace(1)* %out8
78  store i32 %in9, i32 addrspace(1)* %out9
79  store i32 %ina, i32 addrspace(1)* %outa
80  store i32 %inb, i32 addrspace(1)* %outb
81  store i32 %inc, i32 addrspace(1)* %outc
82  store i32 %ind, i32 addrspace(1)* %outd
83  store i32 %ine, i32 addrspace(1)* %oute
84  store i32 %inf, i32 addrspace(1)* %outf
85  ret void
86}
87
88; CHECK:   .name:       num_spilled_vgprs
89; CHECK:   .symbol:     num_spilled_vgprs.kd
90; CHECK:   .vgpr_spill_count: {{13|14}}
91define amdgpu_kernel void @num_spilled_vgprs() #1 {
92  %val0 = load volatile float, float addrspace(1)* @var
93  %val1 = load volatile float, float addrspace(1)* @var
94  %val2 = load volatile float, float addrspace(1)* @var
95  %val3 = load volatile float, float addrspace(1)* @var
96  %val4 = load volatile float, float addrspace(1)* @var
97  %val5 = load volatile float, float addrspace(1)* @var
98  %val6 = load volatile float, float addrspace(1)* @var
99  %val7 = load volatile float, float addrspace(1)* @var
100  %val8 = load volatile float, float addrspace(1)* @var
101  %val9 = load volatile float, float addrspace(1)* @var
102  %val10 = load volatile float, float addrspace(1)* @var
103  %val11 = load volatile float, float addrspace(1)* @var
104  %val12 = load volatile float, float addrspace(1)* @var
105  %val13 = load volatile float, float addrspace(1)* @var
106  %val14 = load volatile float, float addrspace(1)* @var
107  %val15 = load volatile float, float addrspace(1)* @var
108  %val16 = load volatile float, float addrspace(1)* @var
109  %val17 = load volatile float, float addrspace(1)* @var
110  %val18 = load volatile float, float addrspace(1)* @var
111  %val19 = load volatile float, float addrspace(1)* @var
112  %val20 = load volatile float, float addrspace(1)* @var
113  %val21 = load volatile float, float addrspace(1)* @var
114  %val22 = load volatile float, float addrspace(1)* @var
115  %val23 = load volatile float, float addrspace(1)* @var
116  %val24 = load volatile float, float addrspace(1)* @var
117  %val25 = load volatile float, float addrspace(1)* @var
118  %val26 = load volatile float, float addrspace(1)* @var
119  %val27 = load volatile float, float addrspace(1)* @var
120  %val28 = load volatile float, float addrspace(1)* @var
121  %val29 = load volatile float, float addrspace(1)* @var
122  %val30 = load volatile float, float addrspace(1)* @var
123
124  store volatile float %val0, float addrspace(1)* @var
125  store volatile float %val1, float addrspace(1)* @var
126  store volatile float %val2, float addrspace(1)* @var
127  store volatile float %val3, float addrspace(1)* @var
128  store volatile float %val4, float addrspace(1)* @var
129  store volatile float %val5, float addrspace(1)* @var
130  store volatile float %val6, float addrspace(1)* @var
131  store volatile float %val7, float addrspace(1)* @var
132  store volatile float %val8, float addrspace(1)* @var
133  store volatile float %val9, float addrspace(1)* @var
134  store volatile float %val10, float addrspace(1)* @var
135  store volatile float %val11, float addrspace(1)* @var
136  store volatile float %val12, float addrspace(1)* @var
137  store volatile float %val13, float addrspace(1)* @var
138  store volatile float %val14, float addrspace(1)* @var
139  store volatile float %val15, float addrspace(1)* @var
140  store volatile float %val16, float addrspace(1)* @var
141  store volatile float %val17, float addrspace(1)* @var
142  store volatile float %val18, float addrspace(1)* @var
143  store volatile float %val19, float addrspace(1)* @var
144  store volatile float %val20, float addrspace(1)* @var
145  store volatile float %val21, float addrspace(1)* @var
146  store volatile float %val22, float addrspace(1)* @var
147  store volatile float %val23, float addrspace(1)* @var
148  store volatile float %val24, float addrspace(1)* @var
149  store volatile float %val25, float addrspace(1)* @var
150  store volatile float %val26, float addrspace(1)* @var
151  store volatile float %val27, float addrspace(1)* @var
152  store volatile float %val28, float addrspace(1)* @var
153  store volatile float %val29, float addrspace(1)* @var
154  store volatile float %val30, float addrspace(1)* @var
155
156  ret void
157}
158
159; CHECK:  amdhsa.version:
160; CHECK-NEXT: - 1
161; CHECK-NEXT: - 0
162
163attributes #0 = { "amdgpu-num-sgpr"="14" }
164attributes #1 = { "amdgpu-num-vgpr"="20" }
165attributes #2 = { "amdgpu-flat-work-group-size"="1,256" }
166