1; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,WAVE64 %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,WAVE32 %s
3
4; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo14:
5; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4
6; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x3ffc, [[FI]]
7; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MASKED]]
8define amdgpu_kernel void @scratch_buffer_known_high_masklo14() #0 {
9  %alloca = alloca i32, align 4, addrspace(5)
10  store volatile i32 0, i32 addrspace(5)* %alloca
11  %toint = ptrtoint i32 addrspace(5)* %alloca to i32
12  %masked = and i32 %toint, 16383
13  store volatile i32 %masked, i32 addrspace(1)* undef
14  ret void
15}
16
17; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo16:
18; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4
19; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xfffc, [[FI]]
20; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MASKED]]
21define amdgpu_kernel void @scratch_buffer_known_high_masklo16() #0 {
22  %alloca = alloca i32, align 4, addrspace(5)
23  store volatile i32 0, i32 addrspace(5)* %alloca
24  %toint = ptrtoint i32 addrspace(5)* %alloca to i32
25  %masked = and i32 %toint, 65535
26  store volatile i32 %masked, i32 addrspace(1)* undef
27  ret void
28}
29
30; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo17:
31; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4
32; WAVE64-NOT: [[FI]]
33; WAVE64: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FI]]
34
35; WAVE32: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1fffc, [[FI]]
36; WAVE32: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MASKED]]
37define amdgpu_kernel void @scratch_buffer_known_high_masklo17() #0 {
38  %alloca = alloca i32, align 4, addrspace(5)
39  store volatile i32 0, i32 addrspace(5)* %alloca
40  %toint = ptrtoint i32 addrspace(5)* %alloca to i32
41  %masked = and i32 %toint, 131071
42  store volatile i32 %masked, i32 addrspace(1)* undef
43  ret void
44}
45
46; GCN-LABEL: {{^}}scratch_buffer_known_high_mask18:
47; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4
48; GCN-NOT: [[FI]]
49; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FI]]
50define amdgpu_kernel void @scratch_buffer_known_high_mask18() #0 {
51  %alloca = alloca i32, align 4, addrspace(5)
52  store volatile i32 0, i32 addrspace(5)* %alloca
53  %toint = ptrtoint i32 addrspace(5)* %alloca to i32
54  %masked = and i32 %toint, 262143
55  store volatile i32 %masked, i32 addrspace(1)* undef
56  ret void
57}
58
59attributes #0 = { nounwind }
60