1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3
4define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) {
5; SI-LABEL: i1_copy_from_loop:
6; SI:       ; %bb.0: ; %entry
7; SI-NEXT:    s_mov_b32 s6, 0
8; SI-NEXT:    s_mov_b64 s[4:5], 0
9; SI-NEXT:    ; implicit-def: $sgpr8_sgpr9
10; SI-NEXT:    ; implicit-def: $sgpr10_sgpr11
11; SI-NEXT:    s_branch BB0_3
12; SI-NEXT:  BB0_1: ; %Flow1
13; SI-NEXT:    ; in Loop: Header=BB0_3 Depth=1
14; SI-NEXT:    s_or_b64 exec, exec, s[14:15]
15; SI-NEXT:  BB0_2: ; %Flow
16; SI-NEXT:    ; in Loop: Header=BB0_3 Depth=1
17; SI-NEXT:    s_and_b64 s[14:15], exec, s[10:11]
18; SI-NEXT:    s_or_b64 s[4:5], s[14:15], s[4:5]
19; SI-NEXT:    s_andn2_b64 s[8:9], s[8:9], exec
20; SI-NEXT:    s_and_b64 s[12:13], s[12:13], exec
21; SI-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
22; SI-NEXT:    s_andn2_b64 exec, exec, s[4:5]
23; SI-NEXT:    s_cbranch_execz BB0_6
24; SI-NEXT:  BB0_3: ; %for.body
25; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
26; SI-NEXT:    s_or_b64 s[10:11], s[10:11], exec
27; SI-NEXT:    s_cmp_gt_u32 s6, 3
28; SI-NEXT:    v_cmp_lt_u32_e64 s[12:13], s6, 4
29; SI-NEXT:    s_cbranch_scc1 BB0_2
30; SI-NEXT:  ; %bb.4: ; %mid.loop
31; SI-NEXT:    ; in Loop: Header=BB0_3 Depth=1
32; SI-NEXT:    v_mov_b32_e32 v1, s6
33; SI-NEXT:    buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen
34; SI-NEXT:    s_mov_b64 s[12:13], -1
35; SI-NEXT:    s_waitcnt vmcnt(0)
36; SI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v1
37; SI-NEXT:    s_mov_b64 s[10:11], -1
38; SI-NEXT:    s_and_saveexec_b64 s[14:15], vcc
39; SI-NEXT:    s_cbranch_execz BB0_1
40; SI-NEXT:  ; %bb.5: ; %end.loop
41; SI-NEXT:    ; in Loop: Header=BB0_3 Depth=1
42; SI-NEXT:    s_add_i32 s6, s6, 1
43; SI-NEXT:    s_xor_b64 s[10:11], exec, -1
44; SI-NEXT:    s_branch BB0_1
45; SI-NEXT:  BB0_6: ; %for.end
46; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
47; SI-NEXT:    s_and_saveexec_b64 s[0:1], s[8:9]
48; SI-NEXT:    s_cbranch_execz BB0_8
49; SI-NEXT:  ; %bb.7: ; %if
50; SI-NEXT:    exp mrt0 v0, v0, v0, v0 done vm
51; SI-NEXT:  BB0_8: ; %end
52; SI-NEXT:    s_endpgm
53entry:
54  br label %for.body
55
56for.body:
57  %i = phi i32 [0, %entry], [%i.inc, %end.loop]
58  %cc = icmp ult i32 %i, 4
59  br i1 %cc, label %mid.loop, label %for.end
60
61mid.loop:
62  %v = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i32 0, i32 0)
63  %cc2 = fcmp oge float %v, 0.0
64  br i1 %cc2, label %end.loop, label %for.end
65
66end.loop:
67  %i.inc = add i32 %i, 1
68  br label %for.body
69
70for.end:
71  br i1 %cc, label %if, label %end
72
73if:
74  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true)
75  br label %end
76
77end:
78  ret void
79}
80
81declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
82declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
83
84attributes #0 = { nounwind readonly }
85attributes #1 = { nounwind inaccessiblememonly }
86