1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
3
4define amdgpu_kernel void @udiv32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
5; GFX9-LABEL: udiv32_invariant_denom:
6; GFX9:       ; %bb.0: ; %bb
7; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
8; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
9; GFX9-NEXT:    s_mov_b64 s[4:5], 0
10; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
11; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
12; GFX9-NEXT:    s_sub_i32 s3, 0, s2
13; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
14; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
15; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
16; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
17; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
18; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
19; GFX9-NEXT:    v_mov_b32_e32 v1, 0
20; GFX9-NEXT:  BB0_1: ; %bb3
21; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
22; GFX9-NEXT:    v_mul_lo_u32 v2, s5, v0
23; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v0
24; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
25; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v2
26; GFX9-NEXT:    v_not_b32_e32 v5, v2
27; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v5
28; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
29; GFX9-NEXT:    v_add_u32_e32 v3, s4, v3
30; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
31; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
32; GFX9-NEXT:    v_add_u32_e32 v4, s4, v5
33; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
34; GFX9-NEXT:    s_add_u32 s4, s4, 1
35; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
36; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
37; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
38; GFX9-NEXT:    s_addc_u32 s5, s5, 0
39; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
40; GFX9-NEXT:    s_add_u32 s0, s0, 4
41; GFX9-NEXT:    s_addc_u32 s1, s1, 0
42; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
43; GFX9-NEXT:    s_cbranch_scc0 BB0_1
44; GFX9-NEXT:  ; %bb.2: ; %bb2
45; GFX9-NEXT:    s_endpgm
46bb:
47  br label %bb3
48
49bb2:                                              ; preds = %bb3
50  ret void
51
52bb3:                                              ; preds = %bb3, %bb
53  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
54  %tmp4 = udiv i32 %tmp, %arg1
55  %tmp5 = zext i32 %tmp to i64
56  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
57  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
58  %tmp7 = add nuw nsw i32 %tmp, 1
59  %tmp8 = icmp eq i32 %tmp7, 1024
60  br i1 %tmp8, label %bb2, label %bb3
61}
62
63define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
64; GFX9-LABEL: urem32_invariant_denom:
65; GFX9:       ; %bb.0: ; %bb
66; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
67; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
68; GFX9-NEXT:    s_mov_b64 s[4:5], 0
69; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
70; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
71; GFX9-NEXT:    s_sub_i32 s3, 0, s2
72; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
73; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
74; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
75; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
76; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
77; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
78; GFX9-NEXT:    v_mov_b32_e32 v1, 0
79; GFX9-NEXT:  BB1_1: ; %bb3
80; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
81; GFX9-NEXT:    v_mul_lo_u32 v2, s5, v0
82; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v0
83; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
84; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v2
85; GFX9-NEXT:    v_not_b32_e32 v2, v2
86; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v2
87; GFX9-NEXT:    v_add_u32_e32 v3, s4, v3
88; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
89; GFX9-NEXT:    v_add_u32_e32 v2, s4, v2
90; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
91; GFX9-NEXT:    s_add_u32 s4, s4, 1
92; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v2
93; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
94; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
95; GFX9-NEXT:    s_addc_u32 s5, s5, 0
96; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
97; GFX9-NEXT:    s_add_u32 s0, s0, 4
98; GFX9-NEXT:    s_addc_u32 s1, s1, 0
99; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
100; GFX9-NEXT:    s_cbranch_scc0 BB1_1
101; GFX9-NEXT:  ; %bb.2: ; %bb2
102; GFX9-NEXT:    s_endpgm
103bb:
104  br label %bb3
105
106bb2:                                              ; preds = %bb3
107  ret void
108
109bb3:                                              ; preds = %bb3, %bb
110  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
111  %tmp4 = urem i32 %tmp, %arg1
112  %tmp5 = zext i32 %tmp to i64
113  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
114  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
115  %tmp7 = add nuw nsw i32 %tmp, 1
116  %tmp8 = icmp eq i32 %tmp7, 1024
117  br i1 %tmp8, label %bb2, label %bb3
118}
119
120define amdgpu_kernel void @sdiv32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
121; GFX9-LABEL: sdiv32_invariant_denom:
122; GFX9:       ; %bb.0: ; %bb
123; GFX9-NEXT:    s_load_dword s3, s[0:1], 0x2c
124; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
125; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
126; GFX9-NEXT:    s_ashr_i32 s2, s3, 31
127; GFX9-NEXT:    s_add_i32 s3, s3, s2
128; GFX9-NEXT:    s_xor_b32 s3, s3, s2
129; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
130; GFX9-NEXT:    s_sub_i32 s4, 0, s3
131; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
132; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
133; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
134; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
135; GFX9-NEXT:    s_mov_b32 s4, 0
136; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
137; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
138; GFX9-NEXT:    v_mov_b32_e32 v1, 0
139; GFX9-NEXT:  BB2_1: ; %bb3
140; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
141; GFX9-NEXT:    v_mul_hi_u32 v2, s4, v0
142; GFX9-NEXT:    v_mul_lo_u32 v3, v2, s3
143; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
144; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
145; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
146; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
147; GFX9-NEXT:    v_subrev_u32_e32 v4, s3, v3
148; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
149; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
150; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
151; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
152; GFX9-NEXT:    v_xor_b32_e32 v2, s2, v2
153; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v2
154; GFX9-NEXT:    s_add_i32 s4, s4, 1
155; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
156; GFX9-NEXT:    s_add_u32 s0, s0, 4
157; GFX9-NEXT:    s_addc_u32 s1, s1, 0
158; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
159; GFX9-NEXT:    s_cbranch_scc0 BB2_1
160; GFX9-NEXT:  ; %bb.2: ; %bb2
161; GFX9-NEXT:    s_endpgm
162bb:
163  br label %bb3
164
165bb2:                                              ; preds = %bb3
166  ret void
167
168bb3:                                              ; preds = %bb3, %bb
169  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
170  %tmp4 = sdiv i32 %tmp, %arg1
171  %tmp5 = zext i32 %tmp to i64
172  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
173  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
174  %tmp7 = add nuw nsw i32 %tmp, 1
175  %tmp8 = icmp eq i32 %tmp7, 1024
176  br i1 %tmp8, label %bb2, label %bb3
177}
178
179define amdgpu_kernel void @srem32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
180; GFX9-LABEL: srem32_invariant_denom:
181; GFX9:       ; %bb.0: ; %bb
182; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
183; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
184; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
185; GFX9-NEXT:    s_ashr_i32 s3, s2, 31
186; GFX9-NEXT:    s_add_i32 s2, s2, s3
187; GFX9-NEXT:    s_xor_b32 s2, s2, s3
188; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
189; GFX9-NEXT:    s_sub_i32 s3, 0, s2
190; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
191; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
192; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
193; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
194; GFX9-NEXT:    s_mov_b32 s3, 0
195; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
196; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
197; GFX9-NEXT:    v_mov_b32_e32 v1, 0
198; GFX9-NEXT:  BB3_1: ; %bb3
199; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
200; GFX9-NEXT:    v_mul_hi_u32 v2, s3, v0
201; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s2
202; GFX9-NEXT:    v_sub_u32_e32 v2, s3, v2
203; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v2
204; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
205; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
206; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v2
207; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
208; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
209; GFX9-NEXT:    s_add_i32 s3, s3, 1
210; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
211; GFX9-NEXT:    s_add_u32 s0, s0, 4
212; GFX9-NEXT:    s_addc_u32 s1, s1, 0
213; GFX9-NEXT:    s_cmpk_eq_i32 s3, 0x400
214; GFX9-NEXT:    s_cbranch_scc0 BB3_1
215; GFX9-NEXT:  ; %bb.2: ; %bb2
216; GFX9-NEXT:    s_endpgm
217bb:
218  br label %bb3
219
220bb2:                                              ; preds = %bb3
221  ret void
222
223bb3:                                              ; preds = %bb3, %bb
224  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
225  %tmp4 = srem i32 %tmp, %arg1
226  %tmp5 = zext i32 %tmp to i64
227  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
228  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
229  %tmp7 = add nuw nsw i32 %tmp, 1
230  %tmp8 = icmp eq i32 %tmp7, 1024
231  br i1 %tmp8, label %bb2, label %bb3
232}
233
234define amdgpu_kernel void @udiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
235; GFX9-LABEL: udiv16_invariant_denom:
236; GFX9:       ; %bb.0: ; %bb
237; GFX9-NEXT:    s_load_dword s3, s[0:1], 0x2c
238; GFX9-NEXT:    s_mov_b32 s2, 0xffff
239; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
240; GFX9-NEXT:    v_mov_b32_e32 v3, 0
241; GFX9-NEXT:    v_mov_b32_e32 v4, 0
242; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
243; GFX9-NEXT:    s_and_b32 s3, s2, s3
244; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
245; GFX9-NEXT:    s_movk_i32 s3, 0x400
246; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
247; GFX9-NEXT:  BB4_1: ; %bb3
248; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
249; GFX9-NEXT:    v_and_b32_e32 v2, s2, v4
250; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v2
251; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
252; GFX9-NEXT:    v_mov_b32_e32 v7, s5
253; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s4, v5
254; GFX9-NEXT:    v_mul_f32_e32 v2, v8, v1
255; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
256; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
257; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v2
258; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
259; GFX9-NEXT:    v_mad_f32 v2, -v2, v0, v8
260; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, v0
261; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s3, v4
262; GFX9-NEXT:    v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1]
263; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
264; GFX9-NEXT:    global_store_short v[5:6], v2, off
265; GFX9-NEXT:    s_cbranch_vccz BB4_1
266; GFX9-NEXT:  ; %bb.2: ; %bb2
267; GFX9-NEXT:    s_endpgm
268bb:
269  br label %bb3
270
271bb2:                                              ; preds = %bb3
272  ret void
273
274bb3:                                              ; preds = %bb3, %bb
275  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
276  %tmp4 = udiv i16 %tmp, %arg1
277  %tmp5 = zext i16 %tmp to i64
278  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
279  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
280  %tmp7 = add nuw nsw i16 %tmp, 1
281  %tmp8 = icmp eq i16 %tmp7, 1024
282  br i1 %tmp8, label %bb2, label %bb3
283}
284
285define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
286; GFX9-LABEL: urem16_invariant_denom:
287; GFX9:       ; %bb.0: ; %bb
288; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
289; GFX9-NEXT:    s_mov_b32 s4, 0xffff
290; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
291; GFX9-NEXT:    v_mov_b32_e32 v3, 0
292; GFX9-NEXT:    s_movk_i32 s8, 0x400
293; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
294; GFX9-NEXT:    s_and_b32 s5, s4, s2
295; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s5
296; GFX9-NEXT:    v_mov_b32_e32 v4, 0
297; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
298; GFX9-NEXT:  BB5_1: ; %bb3
299; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
300; GFX9-NEXT:    v_and_b32_e32 v2, s4, v4
301; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v2
302; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
303; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
304; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s8, v4
305; GFX9-NEXT:    v_mul_f32_e32 v9, v8, v1
306; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
307; GFX9-NEXT:    v_cvt_u32_f32_e32 v10, v9
308; GFX9-NEXT:    v_mad_f32 v8, -v9, v0, v8
309; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v8|, v0
310; GFX9-NEXT:    v_mov_b32_e32 v7, s7
311; GFX9-NEXT:    v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3]
312; GFX9-NEXT:    v_mul_lo_u32 v8, v8, s5
313; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s6, v5
314; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
315; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
316; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v8
317; GFX9-NEXT:    global_store_short v[5:6], v2, off
318; GFX9-NEXT:    s_cbranch_vccz BB5_1
319; GFX9-NEXT:  ; %bb.2: ; %bb2
320; GFX9-NEXT:    s_endpgm
321bb:
322  br label %bb3
323
324bb2:                                              ; preds = %bb3
325  ret void
326
327bb3:                                              ; preds = %bb3, %bb
328  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
329  %tmp4 = urem i16 %tmp, %arg1
330  %tmp5 = zext i16 %tmp to i64
331  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
332  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
333  %tmp7 = add nuw nsw i16 %tmp, 1
334  %tmp8 = icmp eq i16 %tmp7, 1024
335  br i1 %tmp8, label %bb2, label %bb3
336}
337
338define amdgpu_kernel void @sdiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
339; GFX9-LABEL: sdiv16_invariant_denom:
340; GFX9:       ; %bb.0: ; %bb
341; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
342; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
343; GFX9-NEXT:    v_mov_b32_e32 v3, 0
344; GFX9-NEXT:    s_movk_i32 s3, 0x400
345; GFX9-NEXT:    v_mov_b32_e32 v4, 0
346; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
347; GFX9-NEXT:    s_sext_i32_i16 s2, s2
348; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
349; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
350; GFX9-NEXT:  BB6_1: ; %bb3
351; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
352; GFX9-NEXT:    v_bfe_i32 v5, v4, 0, 16
353; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v4
354; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v5
355; GFX9-NEXT:    v_xor_b32_e32 v8, s2, v5
356; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
357; GFX9-NEXT:    v_mov_b32_e32 v7, s5
358; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s4, v5
359; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
360; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v1
361; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
362; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 30, v8
363; GFX9-NEXT:    v_cvt_i32_f32_e32 v8, v7
364; GFX9-NEXT:    v_mad_f32 v7, -v7, v0, v9
365; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
366; GFX9-NEXT:    v_or_b32_e32 v2, 1, v2
367; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v7|, |v0|
368; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s3, v4
369; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[0:1]
370; GFX9-NEXT:    v_add_u32_e32 v2, v8, v2
371; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
372; GFX9-NEXT:    global_store_short v[5:6], v2, off
373; GFX9-NEXT:    s_cbranch_vccz BB6_1
374; GFX9-NEXT:  ; %bb.2: ; %bb2
375; GFX9-NEXT:    s_endpgm
376bb:
377  br label %bb3
378
379bb2:                                              ; preds = %bb3
380  ret void
381
382bb3:                                              ; preds = %bb3, %bb
383  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
384  %tmp4 = sdiv i16 %tmp, %arg1
385  %tmp5 = zext i16 %tmp to i64
386  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
387  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
388  %tmp7 = add nuw nsw i16 %tmp, 1
389  %tmp8 = icmp eq i16 %tmp7, 1024
390  br i1 %tmp8, label %bb2, label %bb3
391}
392
393define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
394; GFX9-LABEL: srem16_invariant_denom:
395; GFX9:       ; %bb.0: ; %bb
396; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
397; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
398; GFX9-NEXT:    v_mov_b32_e32 v3, 0
399; GFX9-NEXT:    s_movk_i32 s5, 0x400
400; GFX9-NEXT:    v_mov_b32_e32 v4, 0
401; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
402; GFX9-NEXT:    s_sext_i32_i16 s4, s2
403; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s4
404; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
405; GFX9-NEXT:  BB7_1: ; %bb3
406; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
407; GFX9-NEXT:    v_bfe_i32 v7, v4, 0, 16
408; GFX9-NEXT:    v_cvt_f32_i32_e32 v10, v7
409; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v4
410; GFX9-NEXT:    v_xor_b32_e32 v9, s4, v7
411; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
412; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 30, v9
413; GFX9-NEXT:    v_mul_f32_e32 v9, v10, v1
414; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
415; GFX9-NEXT:    v_cvt_i32_f32_e32 v11, v9
416; GFX9-NEXT:    v_mad_f32 v9, -v9, v0, v10
417; GFX9-NEXT:    v_or_b32_e32 v2, 1, v2
418; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v9|, |v0|
419; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[2:3]
420; GFX9-NEXT:    v_add_u32_e32 v2, v11, v2
421; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s4
422; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
423; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s5, v4
424; GFX9-NEXT:    v_mov_b32_e32 v8, s7
425; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s6, v5
426; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
427; GFX9-NEXT:    v_sub_u32_e32 v2, v7, v2
428; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
429; GFX9-NEXT:    global_store_short v[5:6], v2, off
430; GFX9-NEXT:    s_cbranch_vccz BB7_1
431; GFX9-NEXT:  ; %bb.2: ; %bb2
432; GFX9-NEXT:    s_endpgm
433bb:
434  br label %bb3
435
436bb2:                                              ; preds = %bb3
437  ret void
438
439bb3:                                              ; preds = %bb3, %bb
440  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
441  %tmp4 = srem i16 %tmp, %arg1
442  %tmp5 = zext i16 %tmp to i64
443  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
444  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
445  %tmp7 = add nuw nsw i16 %tmp, 1
446  %tmp8 = icmp eq i16 %tmp7, 1024
447  br i1 %tmp8, label %bb2, label %bb3
448}
449