1# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,SICI 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,SICI 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI 4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI,GFX9 5 6--- | 7 define amdgpu_kernel void @div_fmas() { ret void } 8 define amdgpu_kernel void @s_getreg() { ret void } 9 define amdgpu_kernel void @s_setreg() { ret void } 10 define amdgpu_kernel void @vmem_gt_8dw_store() { ret void } 11 define amdgpu_kernel void @readwrite_lane() { ret void } 12 define amdgpu_kernel void @rfe() { ret void } 13 define amdgpu_kernel void @s_movrel() { ret void } 14 define amdgpu_kernel void @v_interp() { ret void } 15 define amdgpu_kernel void @dpp() { ret void } 16... 17--- 18# GCN-LABEL: name: div_fmas 19 20# GCN-LABEL: bb.0: 21# GCN: S_MOV_B64 22# GCN-NOT: S_NOP 23# GCN: V_DIV_FMAS 24 25# GCN-LABEL: bb.1: 26# GCN: V_CMP_EQ_I32 27# GCN: S_NOP 3 28# GCN: V_DIV_FMAS_F32 29 30# GCN-LABEL: bb.2: 31# GCN: V_CMP_EQ_I32 32# GCN: S_NOP 3 33# GCN: V_DIV_FMAS_F32 34 35# GCN-LABEL: bb.3: 36# GCN: V_DIV_SCALE_F32 37# GCN: S_NOP 3 38# GCN: V_DIV_FMAS_F32 39name: div_fmas 40 41body: | 42 bb.0: 43 $vcc = S_MOV_B64 0 44 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 45 S_BRANCH %bb.1 46 47 bb.1: 48 implicit $vcc = V_CMP_EQ_I32_e32 $vgpr1, $vgpr2, implicit $exec 49 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 50 S_BRANCH %bb.2 51 52 bb.2: 53 $vcc = V_CMP_EQ_I32_e64 $vgpr1, $vgpr2, implicit $exec 54 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 55 S_BRANCH %bb.3 56 57 bb.3: 58 $vgpr4, $vcc = V_DIV_SCALE_F32 0, $vgpr1, 0, $vgpr1, 0, $vgpr3, 0, 0, implicit $mode, implicit $exec 59 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 60 S_ENDPGM 0 61 62... 63 64... 65--- 66# GCN-LABEL: name: s_getreg 67 68# GCN-LABEL: bb.0: 69# GCN: S_SETREG 70# GCN: S_NOP 1 71# GCN: S_GETREG 72 73# GCN-LABEL: bb.1: 74# GCN: S_SETREG_IMM32 75# GCN: S_NOP 1 76# GCN: S_GETREG 77 78# GCN-LABEL: bb.2: 79# GCN: S_SETREG 80# GCN: S_NOP 0 81# GCN: S_GETREG 82 83# GCN-LABEL: bb.3: 84# GCN: S_SETREG 85# GCN-NEXT: S_GETREG 86 87name: s_getreg 88 89body: | 90 bb.0: 91 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 92 $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 93 S_BRANCH %bb.1 94 95 bb.1: 96 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode 97 $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 98 S_BRANCH %bb.2 99 100 bb.2: 101 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 102 $sgpr1 = S_MOV_B32 0 103 $sgpr2 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 104 S_BRANCH %bb.3 105 106 bb.3: 107 S_SETREG_B32 $sgpr0, 0, implicit-def $mode, implicit $mode 108 $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 109 S_ENDPGM 0 110... 111 112... 113--- 114# GCN-LABEL: name: s_setreg 115 116# GCN-LABEL: bb.0: 117# GCN: S_SETREG 118# SICI: S_NOP 0 119# VI: S_NOP 1 120# GCN: S_SETREG 121 122# GCN-LABEL: bb.1: 123# GCN: S_SETREG 124# SICI: S_NOP 0 125# VI: S_NOP 1 126# GCN: S_SETREG 127 128# GCN-LABEL: bb.2: 129# GCN: S_SETREG 130# GCN-NEXT: S_SETREG 131 132name: s_setreg 133 134body: | 135 bb.0: 136 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 137 S_SETREG_B32 $sgpr1, 1, implicit-def $mode, implicit $mode 138 S_BRANCH %bb.1 139 140 bb.1: 141 S_SETREG_B32 $sgpr0, 64, implicit-def $mode, implicit $mode 142 S_SETREG_B32 $sgpr1, 128, implicit-def $mode, implicit $mode 143 S_BRANCH %bb.2 144 145 bb.2: 146 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 147 S_SETREG_B32 $sgpr1, 0, implicit-def $mode, implicit $mode 148 S_ENDPGM 0 149... 150 151... 152--- 153# GCN-LABEL: name: vmem_gt_8dw_store 154 155# GCN-LABEL: bb.0: 156# GCN: BUFFER_STORE_DWORD_OFFSET 157# GCN-NEXT: V_MOV_B32 158# GCN: BUFFER_STORE_DWORDX3_OFFSET 159# CIVI: S_NOP 160# GCN-NEXT: V_MOV_B32 161# GCN: BUFFER_STORE_DWORDX4_OFFSET 162# GCN-NEXT: V_MOV_B32 163# GCN: BUFFER_STORE_DWORDX4_OFFSET 164# CIVI: S_NOP 165# GCN-NEXT: V_MOV_B32 166# GCN: BUFFER_STORE_FORMAT_XYZ_OFFSET 167# CIVI: S_NOP 168# GCN-NEXT: V_MOV_B32 169# GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET 170# CIVI: S_NOP 171# GCN-NEXT: V_MOV_B32 172 173# GCN-LABEL: bb.1: 174# GCN: FLAT_STORE_DWORDX2 175# GCN-NEXT: V_MOV_B32 176# GCN: FLAT_STORE_DWORDX3 177# CIVI: S_NOP 178# GCN-NEXT: V_MOV_B32 179# GCN: FLAT_STORE_DWORDX4 180# CIVI: S_NOP 181# GCN-NEXT: V_MOV_B32 182# GCN: FLAT_ATOMIC_CMPSWAP_X2 183# CIVI: S_NOP 184# GCN-NEXT: V_MOV_B32 185# GCN: FLAT_ATOMIC_FCMPSWAP_X2 186# CIVI: S_NOP 187# GCN: V_MOV_B32 188 189name: vmem_gt_8dw_store 190 191body: | 192 bb.0: 193 BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec 194 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 195 BUFFER_STORE_DWORDX3_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 196 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 197 BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec 198 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 199 BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 200 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 201 BUFFER_STORE_FORMAT_XYZ_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 202 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 203 BUFFER_STORE_FORMAT_XYZW_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 204 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 205 BUFFER_ATOMIC_CMPSWAP_X2_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit $exec 206 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 207 S_BRANCH %bb.1 208 209 bb.1: 210 FLAT_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 211 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 212 FLAT_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 213 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 214 FLAT_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 215 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 216 FLAT_ATOMIC_CMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr 217 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 218 FLAT_ATOMIC_FCMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr 219 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 220 S_ENDPGM 0 221 222... 223 224... 225--- 226 227# GCN-LABEL: name: readwrite_lane 228 229# GCN-LABEL: bb.0: 230# GCN: V_ADD_CO_U32 231# GCN: S_NOP 3 232# GCN: V_READLANE_B32 233 234# GCN-LABEL: bb.1: 235# GCN: V_ADD_CO_U32 236# GCN: S_NOP 3 237# GCN: V_WRITELANE_B32 238 239# GCN-LABEL: bb.2: 240# GCN: V_ADD_CO_U32 241# GCN: S_NOP 3 242# GCN: V_READLANE_B32 243 244# GCN-LABEL: bb.3: 245# GCN: V_ADD_CO_U32 246# GCN: S_NOP 3 247# GCN: V_WRITELANE_B32 248 249name: readwrite_lane 250 251body: | 252 bb.0: 253 $vgpr0,$sgpr0_sgpr1 = V_ADD_CO_U32_e64 $vgpr1, $vgpr2, implicit $vcc, 0, implicit $exec 254 $sgpr4 = V_READLANE_B32 $vgpr4, $sgpr0 255 S_BRANCH %bb.1 256 257 bb.1: 258 $vgpr0,$sgpr0_sgpr1 = V_ADD_CO_U32_e64 $vgpr1, $vgpr2, implicit $vcc, 0, implicit $exec 259 $vgpr4 = V_WRITELANE_B32 $sgpr0, $sgpr0, $vgpr4 260 S_BRANCH %bb.2 261 262 bb.2: 263 $vgpr0,implicit $vcc = V_ADD_CO_U32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 264 $sgpr4 = V_READLANE_B32 $vgpr4, $vcc_lo 265 S_BRANCH %bb.3 266 267 bb.3: 268 $m0 = S_MOV_B32 $sgpr4 269 $vgpr0,implicit $vcc = V_ADD_CO_U32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 270 $vgpr4 = V_WRITELANE_B32 $m0, $vcc_lo, $vgpr4 271 S_ENDPGM 0 272 273... 274 275... 276--- 277 278# GCN-LABEL: name: rfe 279 280# GCN-LABEL: bb.0: 281# GCN: S_SETREG 282# VI: S_NOP 283# GCN-NEXT: S_RFE_B64 284 285# GCN-LABEL: bb.1: 286# GCN: S_SETREG 287# GCN-NEXT: S_RFE_B64 288 289name: rfe 290 291body: | 292 bb.0: 293 S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode 294 S_RFE_B64 $sgpr2_sgpr3 295 S_BRANCH %bb.1 296 297 bb.1: 298 S_SETREG_B32 $sgpr0, 0, implicit-def $mode, implicit $mode 299 S_RFE_B64 $sgpr2_sgpr3 300 S_ENDPGM 0 301 302... 303 304... 305--- 306 307# GCN-LABEL: name: s_movrel 308 309# GCN-LABEL: bb.0: 310# GCN: S_MOV_B32 311# GFX9: S_NOP 312# GCN-NEXT: S_MOVRELS_B32 313 314# GCN-LABEL: bb.1: 315# GCN: S_MOV_B32 316# GFX9: S_NOP 317# GCN-NEXT: S_MOVRELS_B64 318 319# GCN-LABEL: bb.2: 320# GCN: S_MOV_B32 321# GFX9: S_NOP 322# GCN-NEXT: S_MOVRELD_B32 323 324# GCN-LABEL: bb.3: 325# GCN: S_MOV_B32 326# GFX9: S_NOP 327# GCN-NEXT: S_MOVRELD_B64 328 329name: s_movrel 330 331body: | 332 bb.0: 333 $m0 = S_MOV_B32 0 334 $sgpr0 = S_MOVRELS_B32 $sgpr0, implicit $m0 335 S_BRANCH %bb.1 336 337 bb.1: 338 $m0 = S_MOV_B32 0 339 $sgpr0_sgpr1 = S_MOVRELS_B64 $sgpr0_sgpr1, implicit $m0 340 S_BRANCH %bb.2 341 342 bb.2: 343 $m0 = S_MOV_B32 0 344 S_MOVRELD_B32 $sgpr0, $sgpr0, implicit $m0 345 S_BRANCH %bb.3 346 347 bb.3: 348 $m0 = S_MOV_B32 0 349 S_MOVRELD_B64 $sgpr0_sgpr1, $sgpr0_sgpr1, implicit $m0 350 S_ENDPGM 0 351... 352 353... 354--- 355 356# GCN-LABEL: name: v_interp 357 358# GCN-LABEL: bb.0: 359# GCN: S_MOV_B32 360# GFX9-NEXT: S_NOP 361# GCN-NEXT: V_INTERP_P1_F32 362 363# GCN-LABEL: bb.1: 364# GCN: S_MOV_B32 365# GFX9-NEXT: S_NOP 366# GCN-NEXT: V_INTERP_P2_F32 367 368# GCN-LABEL: bb.2: 369# GCN: S_MOV_B32 370# GFX9-NEXT: S_NOP 371# GCN-NEXT: V_INTERP_P1_F32_16bank 372 373# GCN-LABEL: bb.3: 374# GCN: S_MOV_B32 375# GFX9-NEXT: S_NOP 376# GCN-NEXT: V_INTERP_MOV_F32 377 378name: v_interp 379 380body: | 381 bb.0: 382 $m0 = S_MOV_B32 0 383 $vgpr0 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec 384 S_BRANCH %bb.1 385 386 bb.1: 387 $m0 = S_MOV_B32 0 388 $vgpr0 = V_INTERP_P2_F32 $vgpr0, $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec 389 S_BRANCH %bb.2 390 391 bb.2: 392 $m0 = S_MOV_B32 0 393 $vgpr0 = V_INTERP_P1_F32_16bank $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec 394 S_BRANCH %bb.3 395 396 bb.3: 397 $m0 = S_MOV_B32 0 398 $vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit $mode, implicit $m0, implicit $exec 399 S_ENDPGM 0 400... 401 402... 403--- 404 405# GCN-LABEL: name: dpp 406 407# VI-LABEL: bb.0: 408# VI: V_MOV_B32_e32 409# VI-NEXT: S_NOP 1 410# VI-NEXT: V_MOV_B32_dpp 411 412# VI-LABEL: bb.1: 413# VI: V_CMPX_EQ_I32_e32 414# VI-NEXT: S_NOP 4 415# VI-NEXT: V_MOV_B32_dpp 416 417name: dpp 418 419body: | 420 bb.0: 421 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 422 $vgpr1 = V_MOV_B32_dpp $vgpr1, $vgpr0, 0, 15, 15, 0, implicit $exec 423 S_BRANCH %bb.1 424 425 bb.1: 426 implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec 427 $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec 428 S_ENDPGM 0 429... 430