1; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
2; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
3; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s
4; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
5; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
6; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=GFX10HSA -check-prefix=ALL %s
7
8; FIXME: align on alloca seems to be ignored for private_segment_alignment
9
10; ALL-LABEL: {{^}}large_alloca_compute_shader:
11
12; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
13; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
14; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
15; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1
16; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
17; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000
18; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000
19; GFX9-DAG: s_mov_b32 s{{[0-9]+}}, 0xe00000
20
21
22; GCNHSA: .amd_kernel_code_t
23
24; GCNHSA: enable_sgpr_private_segment_wave_byte_offset = 1
25; GCNHSA: user_sgpr_count = 8
26; GCNHSA: enable_sgpr_workgroup_id_x = 1
27; GCNHSA: enable_sgpr_workgroup_id_y = 0
28; GCNHSA: enable_sgpr_workgroup_id_z = 0
29; GCNHSA: enable_sgpr_workgroup_info = 0
30; GCNHSA: enable_vgpr_workitem_id = 0
31
32; GCNHSA: enable_sgpr_private_segment_buffer = 1
33; GCNHSA: enable_sgpr_dispatch_ptr = 0
34; GCNHSA: enable_sgpr_queue_ptr = 0
35; GCNHSA: enable_sgpr_kernarg_segment_ptr = 1
36; GCNHSA: enable_sgpr_dispatch_id = 0
37; GCNHSA: enable_sgpr_flat_scratch_init = 1
38; GCNHSA: enable_sgpr_private_segment_size = 0
39; GCNHSA: enable_sgpr_grid_workgroup_count_x = 0
40; GCNHSA: enable_sgpr_grid_workgroup_count_y = 0
41; GCNHSA: enable_sgpr_grid_workgroup_count_z = 0
42; GCNHSA: workitem_private_segment_byte_size = 32772
43; GCNHSA: private_segment_alignment = 4
44; GCNHSA: .end_amd_kernel_code_t
45
46; GFX10HSA: s_add_u32 [[FLAT_SCR_LO:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
47; GFX10HSA-DAG: s_addc_u32 [[FLAT_SCR_HI:s[0-9]+]], s{{[0-9]+}}, 0
48; GFX10HSA-DAG: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), [[FLAT_SCR_LO]]
49; GFX10HSA-DAG: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), [[FLAT_SCR_HI]]
50
51; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen
52; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen
53
54; Scratch size = alloca size + emergency stack slot, align {{.*}}, addrspace(5)
55; ALL: ; ScratchSize: 32772
56define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
57  %large = alloca [8192 x i32], align 4, addrspace(5)
58  %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
59  store volatile i32 %x, i32 addrspace(5)* %gep
60  %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
61  %val = load volatile i32, i32 addrspace(5)* %gep1
62  store volatile i32 %val, i32 addrspace(1)* undef
63  ret void
64}
65
66attributes #0 = { nounwind  }
67