1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI 3 4;CHECK-LABEL: {{^}}buffer_load: 5;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 6;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc 7;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc 8;CHECK: s_waitcnt 9define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { 10main_body: 11 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0) 12 %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0) 13 %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1) 14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 15 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 16 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 17 ret {<4 x float>, <4 x float>, <4 x float>} %r2 18} 19 20;CHECK-LABEL: {{^}}buffer_load_immoffs: 21;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40 22;CHECK: s_waitcnt 23define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { 24main_body: 25 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 40, i1 0, i1 0) 26 ret <4 x float> %data 27} 28 29;CHECK-LABEL: {{^}}buffer_load_immoffs_large: 30;SICI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 offen 31;VI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc 32;VI: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:4 33;CHECK: s_waitcnt 34define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { 35main_body: 36 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0) 37 ret <4 x float> %data 38} 39 40;CHECK-LABEL: {{^}}buffer_load_idx: 41;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen 42;CHECK: s_waitcnt 43define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) { 44main_body: 45 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0) 46 ret <4 x float> %data 47} 48 49;CHECK-LABEL: {{^}}buffer_load_ofs: 50;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen 51;CHECK: s_waitcnt 52define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { 53main_body: 54 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0) 55 ret <4 x float> %data 56} 57 58;CHECK-LABEL: {{^}}buffer_load_ofs_imm: 59;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60 60;CHECK: s_waitcnt 61define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { 62main_body: 63 %ofs = add i32 %1, 60 64 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0) 65 ret <4 x float> %data 66} 67 68;CHECK-LABEL: {{^}}buffer_load_both: 69;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen 70;CHECK: s_waitcnt 71define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) { 72main_body: 73 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0) 74 ret <4 x float> %data 75} 76 77;CHECK-LABEL: {{^}}buffer_load_both_reversed: 78;CHECK: v_mov_b32_e32 v2, v0 79;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen 80;CHECK: s_waitcnt 81define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) { 82main_body: 83 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0) 84 ret <4 x float> %data 85} 86 87;CHECK-LABEL: {{^}}buffer_load_x1: 88;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen 89;CHECK: s_waitcnt 90define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 91main_body: 92 %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) 93 ret float %data 94} 95 96;CHECK-LABEL: {{^}}buffer_load_x2: 97;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen 98;CHECK: s_waitcnt 99define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 100main_body: 101 %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) 102 ret <2 x float> %data 103} 104 105;CHECK-LABEL: {{^}}buffer_load_negative_offset: 106;CHECK: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0 107;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen 108define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) { 109main_body: 110 %ofs.1 = add i32 %ofs, -16 111 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i1 0, i1 0) 112 ret <4 x float> %data 113} 114 115; SI won't merge ds memory operations, because of the signed offset bug, so 116; we only have check lines for VI. 117; CHECK-LABEL: buffer_load_mmo: 118; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 119; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4 120define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) { 121entry: 122 store float 0.0, float addrspace(3)* %lds 123 %val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) 124 %tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4 125 store float 0.0, float addrspace(3)* %tmp2 126 ret float %val 127} 128 129;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged: 130;CHECK-NEXT: %bb. 131;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 132;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 133;CHECK: s_waitcnt 134define amdgpu_ps void @buffer_load_x1_offen_merged(<4 x i32> inreg %rsrc, i32 %a) { 135main_body: 136 %a1 = add i32 %a, 4 137 %a2 = add i32 %a, 8 138 %a3 = add i32 %a, 12 139 %a4 = add i32 %a, 16 140 %a5 = add i32 %a, 28 141 %a6 = add i32 %a, 32 142 %r1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0) 143 %r2 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0) 144 %r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a3, i1 0, i1 0) 145 %r4 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a4, i1 0, i1 0) 146 %r5 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a5, i1 0, i1 0) 147 %r6 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a6, i1 0, i1 0) 148 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 149 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 150 ret void 151} 152 153;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc: 154;CHECK-NEXT: %bb. 155;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}} 156;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}} 157;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}} 158;CHECK: s_waitcnt 159define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) { 160main_body: 161 %a1 = add i32 %a, 4 162 %a2 = add i32 %a, 8 163 %a3 = add i32 %a, 12 164 %a4 = add i32 %a, 16 165 %a5 = add i32 %a, 28 166 %a6 = add i32 %a, 32 167 %r1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0) 168 %r2 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0) 169 %r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a3, i1 1, i1 0) 170 %r4 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a4, i1 1, i1 0) 171 %r5 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a5, i1 1, i1 1) 172 %r6 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a6, i1 1, i1 1) 173 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 174 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 175 ret void 176} 177 178;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged: 179;CHECK-NEXT: %bb. 180;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 181;CHECK: s_waitcnt 182define amdgpu_ps void @buffer_load_x2_offen_merged(<4 x i32> inreg %rsrc, i32 %a) { 183main_body: 184 %a1 = add i32 %a, 4 185 %a2 = add i32 %a, 12 186 %vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0) 187 %vr2 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0) 188 %r1 = extractelement <2 x float> %vr1, i32 0 189 %r2 = extractelement <2 x float> %vr1, i32 1 190 %r3 = extractelement <2 x float> %vr2, i32 0 191 %r4 = extractelement <2 x float> %vr2, i32 1 192 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 193 ret void 194} 195 196;CHECK-LABEL: {{^}}buffer_load_x3_offen_merged: 197;CHECK-NEXT: %bb. 198;VI-NEXT: buffer_load_dwordx3 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 199;CHECK: s_waitcnt 200define amdgpu_ps void @buffer_load_x3_offen_merged(<4 x i32> inreg %rsrc, i32 %a) { 201main_body: 202 %a1 = add i32 %a, 4 203 %a2 = add i32 %a, 12 204 %vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0) 205 %r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0) 206 %r1 = extractelement <2 x float> %vr1, i32 0 207 %r2 = extractelement <2 x float> %vr1, i32 1 208 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float undef, i1 true, i1 true) 209 ret void 210} 211 212;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged: 213;CHECK-NEXT: %bb. 214;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 215;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28 216;CHECK: s_waitcnt 217define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { 218main_body: 219 %r1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0) 220 %r2 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 221 %r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0) 222 %r4 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0) 223 %r5 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 28, i1 0, i1 0) 224 %r6 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 32, i1 0, i1 0) 225 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 226 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 227 ret void 228} 229 230;CHECK-LABEL: {{^}}buffer_load_x2_offset_merged: 231;CHECK-NEXT: %bb. 232;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 233;CHECK: s_waitcnt 234define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) { 235main_body: 236 %vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0) 237 %vr2 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0) 238 %r1 = extractelement <2 x float> %vr1, i32 0 239 %r2 = extractelement <2 x float> %vr1, i32 1 240 %r3 = extractelement <2 x float> %vr2, i32 0 241 %r4 = extractelement <2 x float> %vr2, i32 1 242 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 243 ret void 244} 245 246;CHECK-LABEL: {{^}}buffer_load_x3_offset_merged: 247;CHECK-NEXT: %bb. 248;VI-NEXT: buffer_load_dwordx3 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 249;CHECK: s_waitcnt 250define amdgpu_ps void @buffer_load_x3_offset_merged(<4 x i32> inreg %rsrc) { 251main_body: 252 %vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0) 253 %r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0) 254 %r1 = extractelement <2 x float> %vr1, i32 0 255 %r2 = extractelement <2 x float> %vr1, i32 1 256 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float undef, i1 true, i1 true) 257 ret void 258} 259 260;CHECK-LABEL: {{^}}buffer_load_ubyte: 261;CHECK-NEXT: %bb. 262;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8 263;CHECK-NEXT: s_waitcnt vmcnt(0) 264;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 265;CHECK-NEXT: ; return to shader part epilog 266define amdgpu_ps float @buffer_load_ubyte(<4 x i32> inreg %rsrc) { 267main_body: 268 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 269 %val = uitofp i8 %tmp to float 270 ret float %val 271} 272 273;CHECK-LABEL: {{^}}buffer_load_ushort: 274;CHECK-NEXT: %bb. 275;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 offset:16 276;CHECK-NEXT: s_waitcnt vmcnt(0) 277;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0 278;CHECK-NEXT: ; return to shader part epilog 279define amdgpu_ps float @buffer_load_ushort(<4 x i32> inreg %rsrc) { 280main_body: 281 %tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0) 282 %tmp2 = zext i16 %tmp to i32 283 %val = uitofp i32 %tmp2 to float 284 ret float %val 285} 286 287;CHECK-LABEL: {{^}}buffer_load_sbyte: 288;CHECK-NEXT: %bb. 289;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 offset:8 290;CHECK-NEXT: s_waitcnt vmcnt(0) 291;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 292;CHECK-NEXT: ; return to shader part epilog 293define amdgpu_ps float @buffer_load_sbyte(<4 x i32> inreg %rsrc) { 294main_body: 295 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 296 %tmp2 = sext i8 %tmp to i32 297 %val = sitofp i32 %tmp2 to float 298 ret float %val 299} 300 301;CHECK-LABEL: {{^}}buffer_load_sshort: 302;CHECK-NEXT: %bb. 303;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 offset:16 304;CHECK-NEXT: s_waitcnt vmcnt(0) 305;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 306;CHECK-NEXT: ; return to shader part epilog 307define amdgpu_ps float @buffer_load_sshort(<4 x i32> inreg %rsrc) { 308main_body: 309 %tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0) 310 %tmp2 = sext i16 %tmp to i32 311 %val = sitofp i32 %tmp2 to float 312 ret float %val 313} 314 315;CHECK-LABEL: {{^}}buffer_load_ubyte_bitcast: 316;CHECK-NEXT: %bb. 317;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8 318;CHECK-NEXT: s_waitcnt vmcnt(0) 319;CHECK-NEXT: ; return to shader part epilog 320define amdgpu_ps float @buffer_load_ubyte_bitcast(<4 x i32> inreg %rsrc) { 321main_body: 322 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 323 %tmp2 = zext i8 %tmp to i32 324 %val = bitcast i32 %tmp2 to float 325 ret float %val 326} 327 328;CHECK-LABEL: {{^}}buffer_load_ushort_bitcast: 329;CHECK-NEXT: %bb. 330;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 offset:8 331;CHECK-NEXT: s_waitcnt vmcnt(0) 332;CHECK-NEXT: ; return to shader part epilog 333define amdgpu_ps float @buffer_load_ushort_bitcast(<4 x i32> inreg %rsrc) { 334main_body: 335 %tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 336 %tmp2 = zext i16 %tmp to i32 337 %val = bitcast i32 %tmp2 to float 338 ret float %val 339} 340 341;CHECK-LABEL: {{^}}buffer_load_sbyte_bitcast: 342;CHECK-NEXT: %bb. 343;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 offset:8 344;CHECK-NEXT: s_waitcnt vmcnt(0) 345;CHECK-NEXT: ; return to shader part epilog 346define amdgpu_ps float @buffer_load_sbyte_bitcast(<4 x i32> inreg %rsrc) { 347main_body: 348 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 349 %tmp2 = sext i8 %tmp to i32 350 %val = bitcast i32 %tmp2 to float 351 ret float %val 352} 353 354;CHECK-LABEL: {{^}}buffer_load_sshort_bitcast: 355;CHECK-NEXT: %bb. 356;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 offset:8 357;CHECK-NEXT: s_waitcnt vmcnt(0) 358;CHECK-NEXT: ; return to shader part epilog 359define amdgpu_ps float @buffer_load_sshort_bitcast(<4 x i32> inreg %rsrc) { 360main_body: 361 %tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 362 %tmp2 = sext i16 %tmp to i32 363 %val = bitcast i32 %tmp2 to float 364 ret float %val 365} 366 367;CHECK-LABEL: {{^}}buffer_load_ubyte_mul_bitcast: 368;CHECK-NEXT: %bb. 369;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8 370;CHECK-NEXT: s_waitcnt vmcnt(0) 371;CHECK-NEXT: v_mul_u32_u24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}} 372;CHECK-NEXT: ; return to shader part epilog 373define amdgpu_ps float @buffer_load_ubyte_mul_bitcast(<4 x i32> inreg %rsrc) { 374main_body: 375 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 376 %tmp2 = zext i8 %tmp to i32 377 %tmp3 = mul i32 %tmp2, 255 378 %val = bitcast i32 %tmp3 to float 379 ret float %val 380} 381 382;CHECK-LABEL: {{^}}buffer_load_ushort_mul_bitcast: 383;CHECK-NEXT: %bb. 384;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 offset:8 385;CHECK-NEXT: s_waitcnt vmcnt(0) 386;CHECK-NEXT: v_mul_u32_u24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}} 387;CHECK-NEXT: ; return to shader part epilog 388define amdgpu_ps float @buffer_load_ushort_mul_bitcast(<4 x i32> inreg %rsrc) { 389main_body: 390 %tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 391 %tmp2 = zext i16 %tmp to i32 392 %tmp3 = mul i32 %tmp2, 255 393 %val = bitcast i32 %tmp3 to float 394 ret float %val 395} 396 397;CHECK-LABEL: {{^}}buffer_load_sbyte_mul_bitcast: 398;CHECK-NEXT: %bb. 399;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 offset:8 400;CHECK-NEXT: s_waitcnt vmcnt(0) 401;CHECK-NEXT: v_mul_i32_i24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}} 402;CHECK-NEXT: ; return to shader part epilog 403define amdgpu_ps float @buffer_load_sbyte_mul_bitcast(<4 x i32> inreg %rsrc) { 404main_body: 405 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 406 %tmp2 = sext i8 %tmp to i32 407 %tmp3 = mul i32 %tmp2, 255 408 %val = bitcast i32 %tmp3 to float 409 ret float %val 410} 411 412;CHECK-LABEL: {{^}}buffer_load_sshort_mul_bitcast: 413;CHECK-NEXT: %bb. 414;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 offset:8 415;CHECK-NEXT: s_waitcnt vmcnt(0) 416;CHECK-NEXT: v_mul_i32_i24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}} 417;CHECK-NEXT: ; return to shader part epilog 418define amdgpu_ps float @buffer_load_sshort_mul_bitcast(<4 x i32> inreg %rsrc) { 419main_body: 420 %tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 421 %tmp2 = sext i16 %tmp to i32 422 %tmp3 = mul i32 %tmp2, 255 423 %val = bitcast i32 %tmp3 to float 424 ret float %val 425} 426 427;CHECK-LABEL: {{^}}buffer_load_sbyte_type_check: 428;CHECK-NEXT: %bb. 429;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8 430;CHECK-NEXT: s_waitcnt vmcnt(0) 431;CHECK-NEXT: v_bfe_i32 v{{[0-9]}}, v{{[0-9]}}, 0, 5 432;CHECK-NEXT: ; return to shader part epilog 433define amdgpu_ps float @buffer_load_sbyte_type_check(<4 x i32> inreg %rsrc) { 434main_body: 435 %tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0) 436 %tmp2 = zext i8 %tmp to i32 437 %tmp3 = shl i32 %tmp2, 27 438 %tmp4 = ashr i32 %tmp3, 27 439 %val = bitcast i32 %tmp4 to float 440 ret float %val 441} 442 443; Make sure a frame index folding doessn't crash on a MUBUF not used 444; for stack access. 445 446; CHECK-LABEL: {{^}}no_fold_fi_imm_soffset: 447; CHECK: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} 448; CHECK-NEXT: buffer_load_dword v0, [[FI]], s{{\[[0-9]+:[0-9]+\]}}, 0 idxen 449define amdgpu_ps float @no_fold_fi_imm_soffset(<4 x i32> inreg %rsrc) { 450 %alloca = alloca i32, addrspace(5) 451 %alloca.cast = ptrtoint i32 addrspace(5)* %alloca to i32 452 453 %ret.val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %alloca.cast, i32 0, i1 false, i1 false) 454 ret float %ret.val 455} 456 457; CHECK-LABEL: {{^}}no_fold_fi_reg_soffset: 458; CHECK-DAG: v_mov_b32_e32 v[[FI:[0-9]+]], 4{{$}} 459; CHECK-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s 460; CHECK: buffer_load_dword v0, v{{\[}}[[FI]]:[[HI]] 461define amdgpu_ps float @no_fold_fi_reg_soffset(<4 x i32> inreg %rsrc, i32 inreg %soffset) { 462 %alloca = alloca i32, addrspace(5) 463 %alloca.cast = ptrtoint i32 addrspace(5)* %alloca to i32 464 465 %ret.val = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %alloca.cast, i32 %soffset, i1 false, i1 false) 466 ret float %ret.val 467} 468 469declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 470declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0 471declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0 472declare i8 @llvm.amdgcn.buffer.load.i8(<4 x i32>, i32, i32, i1, i1) #0 473declare i16 @llvm.amdgcn.buffer.load.i16(<4 x i32>, i32, i32, i1, i1) #0 474declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 475 476attributes #0 = { nounwind readonly } 477