1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 3; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 4; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 5 6; FUNC-LABEL: {{^}}ds_ordered_swap: 7; GCN: s_mov_b32 m0, s0 8; VIGFX9-NEXT: s_nop 0 9; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v0 offset:4868 gds 10; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 11define amdgpu_cs float @ds_ordered_swap(i32 addrspace(2)* inreg %gds, i32 %value) { 12 %val = call i32@llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 13 %r = bitcast i32 %val to float 14 ret float %r 15} 16 17; FUNC-LABEL: {{^}}ds_ordered_swap_conditional: 18; GCN: v_cmp_ne_u32_e32 vcc, 0, v[[VALUE:[0-9]+]] 19; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc 20; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0 21; GCN: s_cbranch_execz [[BB:BB._.]] 22; GCN: s_mov_b32 m0, s0 23; VIGFX9-NEXT: s_nop 0 24; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[VALUE]] offset:4868 gds 25; GCN-NEXT: [[BB]]: 26; // Wait for expcnt(0) before modifying EXEC 27; GCN-NEXT: s_waitcnt expcnt(0) 28; GCN-NEXT: s_or_b64 exec, exec, s[[SAVED]] 29; GCN-NEXT: s_waitcnt lgkmcnt(0) 30define amdgpu_cs float @ds_ordered_swap_conditional(i32 addrspace(2)* inreg %gds, i32 %value) { 31entry: 32 %c = icmp ne i32 %value, 0 33 br i1 %c, label %if-true, label %endif 34 35if-true: 36 %val = call i32@llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 37 br label %endif 38 39endif: 40 %v = phi i32 [ %val, %if-true ], [ undef, %entry ] 41 %r = bitcast i32 %v to float 42 ret float %r 43} 44 45declare i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* nocapture, i32, i32, i32, i1, i32, i1, i1) 46