1; RUN: llc -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
4; RUN: llc -march=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
5
6declare float @llvm.amdgcn.fmad.ftz.f32(float %a, float %b, float %c)
7
8; GCN-LABEL: {{^}}mad_f32:
9; GCN:  v_ma{{[dc]}}_f32
10define amdgpu_kernel void @mad_f32(
11    float addrspace(1)* %r,
12    float addrspace(1)* %a,
13    float addrspace(1)* %b,
14    float addrspace(1)* %c) {
15  %a.val = load float, float addrspace(1)* %a
16  %b.val = load float, float addrspace(1)* %b
17  %c.val = load float, float addrspace(1)* %c
18  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float %a.val, float %b.val, float %c.val)
19  store float %r.val, float addrspace(1)* %r
20  ret void
21}
22
23; GCN-LABEL: {{^}}mad_f32_imm_a:
24; GCN: v_madmk_f32 {{v[0-9]+}}, {{v[0-9]+}}, 0x41000000,
25define amdgpu_kernel void @mad_f32_imm_a(
26    float addrspace(1)* %r,
27    float addrspace(1)* %b,
28    float addrspace(1)* %c) {
29  %b.val = load float, float addrspace(1)* %b
30  %c.val = load float, float addrspace(1)* %c
31  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float 8.0, float %b.val, float %c.val)
32  store float %r.val, float addrspace(1)* %r
33  ret void
34}
35
36; GCN-LABEL: {{^}}mad_f32_imm_b:
37; GCN: v_mov_b32_e32 [[KB:v[0-9]+]], 0x41000000
38; GCN: v_mac_f32_e32 {{v[0-9]+}}, {{[s][0-9]+}}, [[KB]]
39define amdgpu_kernel void @mad_f32_imm_b(
40    float addrspace(1)* %r,
41    float addrspace(1)* %a,
42    float addrspace(1)* %c) {
43  %a.val = load float, float addrspace(1)* %a
44  %c.val = load float, float addrspace(1)* %c
45  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float %a.val, float 8.0, float %c.val)
46  store float %r.val, float addrspace(1)* %r
47  ret void
48}
49
50; GCN-LABEL: {{^}}mad_f32_imm_c:
51; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x41000000
52; GCN: s_load_dword [[A:s[0-9]+]]
53; GCN: s_load_dword [[B:s[0-9]+]]
54; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
55; GCN: v_mac_f32_e32 [[C]], {{s[0-9]+}}, [[VB]]{{$}}
56define amdgpu_kernel void @mad_f32_imm_c(
57    float addrspace(1)* %r,
58    float addrspace(1)* %a,
59    float addrspace(1)* %b) {
60  %a.val = load float, float addrspace(1)* %a
61  %b.val = load float, float addrspace(1)* %b
62  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float %a.val, float %b.val, float 8.0)
63  store float %r.val, float addrspace(1)* %r
64  ret void
65}
66
67; GCN-LABEL: {{^}}mad_f32_neg_b:
68; GCN:  v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
69define amdgpu_kernel void @mad_f32_neg_b(
70    float addrspace(1)* %r,
71    float addrspace(1)* %a,
72    float addrspace(1)* %b,
73    float addrspace(1)* %c) {
74  %a.val = load float, float addrspace(1)* %a
75  %b.val = load float, float addrspace(1)* %b
76  %c.val = load float, float addrspace(1)* %c
77  %neg.b = fsub float -0.0, %b.val
78  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float %a.val, float %neg.b, float %c.val)
79  store float %r.val, float addrspace(1)* %r
80  ret void
81}
82
83; GCN-LABEL: {{^}}mad_f32_abs_b:
84; GCN:  v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}
85define amdgpu_kernel void @mad_f32_abs_b(
86    float addrspace(1)* %r,
87    float addrspace(1)* %a,
88    float addrspace(1)* %b,
89    float addrspace(1)* %c) {
90  %a.val = load float, float addrspace(1)* %a
91  %b.val = load float, float addrspace(1)* %b
92  %c.val = load float, float addrspace(1)* %c
93  %abs.b = call float @llvm.fabs.f32(float %b.val)
94  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float %a.val, float %abs.b, float %c.val)
95  store float %r.val, float addrspace(1)* %r
96  ret void
97}
98
99; GCN-LABEL: {{^}}mad_f32_neg_abs_b:
100; GCN:  v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}}
101define amdgpu_kernel void @mad_f32_neg_abs_b(
102    float addrspace(1)* %r,
103    float addrspace(1)* %a,
104    float addrspace(1)* %b,
105    float addrspace(1)* %c) {
106  %a.val = load float, float addrspace(1)* %a
107  %b.val = load float, float addrspace(1)* %b
108  %c.val = load float, float addrspace(1)* %c
109  %abs.b = call float @llvm.fabs.f32(float %b.val)
110  %neg.abs.b = fsub float -0.0, %abs.b
111  %r.val = call float @llvm.amdgcn.fmad.ftz.f32(float %a.val, float %neg.abs.b, float %c.val)
112  store float %r.val, float addrspace(1)* %r
113  ret void
114}
115
116declare float @llvm.fabs.f32(float)
117