1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}test_fmed3_f16:
4; GCN: v_med3_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
5define amdgpu_kernel void @test_fmed3_f16(half addrspace(1)* %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
6  %src0.f16 = trunc i32 %src0.arg to i16
7  %src0 = bitcast i16 %src0.f16 to half
8  %src1.f16 = trunc i32 %src1.arg to i16
9  %src1 = bitcast i16 %src1.f16 to half
10  %src2.f16 = trunc i32 %src2.arg to i16
11  %src2 = bitcast i16 %src2.f16 to half
12  %mad = call half @llvm.amdgcn.fmed3.f16(half %src0, half %src1, half %src2)
13  store half %mad, half addrspace(1)* %out
14  ret void
15}
16
17; GCN-LABEL: {{^}}test_fmed3_srcmods_f16:
18; GCN: v_med3_f16 v{{[0-9]+}}, -s{{[0-9]+}}, |v{{[0-9]+}}|, -|v{{[0-9]+}}|
19define amdgpu_kernel void @test_fmed3_srcmods_f16(half addrspace(1)* %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
20  %src0.f16 = trunc i32 %src0.arg to i16
21  %src0 = bitcast i16 %src0.f16 to half
22  %src1.f16 = trunc i32 %src1.arg to i16
23  %src1 = bitcast i16 %src1.f16 to half
24  %src2.f16 = trunc i32 %src2.arg to i16
25  %src2 = bitcast i16 %src2.f16 to half
26  %src0.fneg = fsub half -0.0, %src0
27  %src1.fabs = call half @llvm.fabs.f16(half %src1)
28  %src2.fabs = call half @llvm.fabs.f16(half %src2)
29  %src2.fneg.fabs = fsub half -0.0, %src2.fabs
30  %mad = call half @llvm.amdgcn.fmed3.f16(half %src0.fneg, half %src1.fabs, half %src2.fneg.fabs)
31  store half %mad, half addrspace(1)* %out
32  ret void
33}
34
35declare half @llvm.amdgcn.fmed3.f16(half, half, half) #0
36declare half @llvm.fabs.f16(half) #0
37
38attributes #0 = { nounwind readnone }
39attributes #1 = { nounwind }
40