1; RUN: llc -march=amdgcn -mcpu=tahiti  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX6 %s
2; RUN: llc -march=amdgcn -mcpu=tonga   -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX8 %s
3; RUN: llc -march=amdgcn -mcpu=gfx900  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX9 %s
4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX101 %s
5; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOMADMACF32,GFX103 %s
6
7; GCN-LABEL: {{^}}test_mul_legacy_f32:
8; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
9define amdgpu_kernel void @test_mul_legacy_f32(float addrspace(1)* %out, float %a, float %b) #0 {
10  %result = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
11  store float %result, float addrspace(1)* %out, align 4
12  ret void
13}
14
15; GCN-LABEL: {{^}}test_mul_legacy_undef0_f32:
16; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
17define amdgpu_kernel void @test_mul_legacy_undef0_f32(float addrspace(1)* %out, float %a) #0 {
18  %result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a)
19  store float %result, float addrspace(1)* %out, align 4
20  ret void
21}
22
23; GCN-LABEL: {{^}}test_mul_legacy_undef1_f32:
24; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
25define amdgpu_kernel void @test_mul_legacy_undef1_f32(float addrspace(1)* %out, float %a) #0 {
26  %result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef)
27  store float %result, float addrspace(1)* %out, align 4
28  ret void
29}
30
31; GCN-LABEL: {{^}}test_mul_legacy_fabs_f32:
32; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, |s{{[0-9]+}}|, |{{[sv][0-9]+}}|
33define amdgpu_kernel void @test_mul_legacy_fabs_f32(float addrspace(1)* %out, float %a, float %b) #0 {
34  %a.fabs = call float @llvm.fabs.f32(float %a)
35  %b.fabs = call float @llvm.fabs.f32(float %b)
36  %result = call float @llvm.amdgcn.fmul.legacy(float %a.fabs, float %b.fabs)
37  store float %result, float addrspace(1)* %out, align 4
38  ret void
39}
40
41; Don't form mad/mac instructions because they don't support denormals.
42; GCN-LABEL: {{^}}test_add_mul_legacy_f32:
43; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
44; GCN: v_add_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
45define amdgpu_kernel void @test_add_mul_legacy_f32(float addrspace(1)* %out, float %a, float %b, float %c) #0 {
46  %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
47  %add = fadd float %mul, %c
48  store float %add, float addrspace(1)* %out, align 4
49  ret void
50}
51
52; GCN-LABEL: {{^}}test_mad_legacy_f32:
53; GFX6: v_mac_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
54; GFX8: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
55; GFX9: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
56; GFX101: v_mac_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
57; GFX103: v_mul_legacy_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
58; GFX103: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
59define amdgpu_kernel void @test_mad_legacy_f32(float addrspace(1)* %out, float %a, float %b, float %c) #2 {
60  %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
61  %add = fadd float %mul, %c
62  store float %add, float addrspace(1)* %out, align 4
63  ret void
64}
65
66; GCN-LABEL: {{^}}test_mad_legacy_fneg_f32:
67; MADMACF32: v_mad_legacy_f32 v{{[0-9]+}}, -s{{[0-9]+}}, -{{[sv][0-9]+}}, v{{[0-9]+}}
68; NOMADMACF32: v_mul_legacy_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}, -s{{[0-9]+}}
69; NOMADMACF32: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
70define amdgpu_kernel void @test_mad_legacy_fneg_f32(float addrspace(1)* %out, float %a, float %b, float %c) #2 {
71  %a.fneg = fneg float %a
72  %b.fneg = fneg float %b
73  %mul = call float @llvm.amdgcn.fmul.legacy(float %a.fneg, float %b.fneg)
74  %add = fadd float %mul, %c
75  store float %add, float addrspace(1)* %out, align 4
76  ret void
77}
78
79declare float @llvm.fabs.f32(float) #1
80declare float @llvm.amdgcn.fmul.legacy(float, float) #1
81
82attributes #0 = { nounwind }
83attributes #1 = { nounwind readnone }
84attributes #2 = { nounwind "denormal-fp-math"="preserve-sign" }
85