1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s 3 4define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) { 5; GFX10-LABEL: sample_d_1d: 6; GFX10: ; %bb.0: ; %main_body 7; GFX10-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 8; GFX10-NEXT: s_waitcnt vmcnt(0) 9; GFX10-NEXT: ; return to shader part epilog 10main_body: 11 %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 12 ret <4 x float> %v 13} 14 15define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 16; GFX10-LABEL: sample_d_2d: 17; GFX10: ; %bb.0: ; %main_body 18; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff 19; GFX10-NEXT: v_and_b32_e32 v2, v7, v2 20; GFX10-NEXT: v_and_b32_e32 v0, v7, v0 21; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 22; GFX10-NEXT: v_lshl_or_b32 v3, v1, 16, v0 23; GFX10-NEXT: image_sample_d_g16 v[0:3], [v3, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 24; GFX10-NEXT: s_waitcnt vmcnt(0) 25; GFX10-NEXT: ; return to shader part epilog 26main_body: 27 %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 28 ret <4 x float> %v 29} 30 31define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) { 32; GFX10-LABEL: sample_d_3d: 33; GFX10: ; %bb.0: ; %main_body 34; GFX10-NEXT: v_mov_b32_e32 v9, 0xffff 35; GFX10-NEXT: v_and_b32_e32 v3, v9, v3 36; GFX10-NEXT: v_and_b32_e32 v0, v9, v0 37; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 38; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 39; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v6, v7, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D 40; GFX10-NEXT: s_waitcnt vmcnt(0) 41; GFX10-NEXT: ; return to shader part epilog 42main_body: 43 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 44 ret <4 x float> %v 45} 46 47define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) { 48; GFX10-LABEL: sample_c_d_1d: 49; GFX10: ; %bb.0: ; %main_body 50; GFX10-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 51; GFX10-NEXT: s_waitcnt vmcnt(0) 52; GFX10-NEXT: ; return to shader part epilog 53main_body: 54 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 55 ret <4 x float> %v 56} 57 58define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 59; GFX10-LABEL: sample_c_d_2d: 60; GFX10: ; %bb.0: ; %main_body 61; GFX10-NEXT: v_mov_b32_e32 v10, 0xffff 62; GFX10-NEXT: v_and_b32_e32 v3, v10, v3 63; GFX10-NEXT: v_and_b32_e32 v1, v10, v1 64; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 65; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 66; GFX10-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 67; GFX10-NEXT: s_waitcnt vmcnt(0) 68; GFX10-NEXT: ; return to shader part epilog 69main_body: 70 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 71 ret <4 x float> %v 72} 73 74define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) { 75; GFX10-LABEL: sample_d_cl_1d: 76; GFX10: ; %bb.0: ; %main_body 77; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 78; GFX10-NEXT: s_waitcnt vmcnt(0) 79; GFX10-NEXT: ; return to shader part epilog 80main_body: 81 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 82 ret <4 x float> %v 83} 84 85define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 86; GFX10-LABEL: sample_d_cl_2d: 87; GFX10: ; %bb.0: ; %main_body 88; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff 89; GFX10-NEXT: v_and_b32_e32 v2, v7, v2 90; GFX10-NEXT: v_and_b32_e32 v0, v7, v0 91; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 92; GFX10-NEXT: v_lshl_or_b32 v3, v1, 16, v0 93; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], [v3, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 94; GFX10-NEXT: s_waitcnt vmcnt(0) 95; GFX10-NEXT: ; return to shader part epilog 96main_body: 97 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 98 ret <4 x float> %v 99} 100 101define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) { 102; GFX10-LABEL: sample_c_d_cl_1d: 103; GFX10: ; %bb.0: ; %main_body 104; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 105; GFX10-NEXT: s_waitcnt vmcnt(0) 106; GFX10-NEXT: ; return to shader part epilog 107main_body: 108 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 109 ret <4 x float> %v 110} 111 112define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 113; GFX10-LABEL: sample_c_d_cl_2d: 114; GFX10: ; %bb.0: ; %main_body 115; GFX10-NEXT: v_mov_b32_e32 v8, 0xffff 116; GFX10-NEXT: v_and_b32_e32 v3, v8, v3 117; GFX10-NEXT: v_and_b32_e32 v1, v8, v1 118; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 119; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 120; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 121; GFX10-NEXT: s_waitcnt vmcnt(0) 122; GFX10-NEXT: ; return to shader part epilog 123main_body: 124 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 125 ret <4 x float> %v 126} 127 128define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) { 129; GFX10-LABEL: sample_cd_1d: 130; GFX10: ; %bb.0: ; %main_body 131; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 132; GFX10-NEXT: s_waitcnt vmcnt(0) 133; GFX10-NEXT: ; return to shader part epilog 134main_body: 135 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 136 ret <4 x float> %v 137} 138 139define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 140; GFX10-LABEL: sample_cd_2d: 141; GFX10: ; %bb.0: ; %main_body 142; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff 143; GFX10-NEXT: v_and_b32_e32 v2, v7, v2 144; GFX10-NEXT: v_and_b32_e32 v0, v7, v0 145; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 146; GFX10-NEXT: v_lshl_or_b32 v3, v1, 16, v0 147; GFX10-NEXT: image_sample_cd_g16 v[0:3], [v3, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 148; GFX10-NEXT: s_waitcnt vmcnt(0) 149; GFX10-NEXT: ; return to shader part epilog 150main_body: 151 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 152 ret <4 x float> %v 153} 154 155define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) { 156; GFX10-LABEL: sample_c_cd_1d: 157; GFX10: ; %bb.0: ; %main_body 158; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 159; GFX10-NEXT: s_waitcnt vmcnt(0) 160; GFX10-NEXT: ; return to shader part epilog 161main_body: 162 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 163 ret <4 x float> %v 164} 165 166define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 167; GFX10-LABEL: sample_c_cd_2d: 168; GFX10: ; %bb.0: ; %main_body 169; GFX10-NEXT: v_mov_b32_e32 v10, 0xffff 170; GFX10-NEXT: v_and_b32_e32 v3, v10, v3 171; GFX10-NEXT: v_and_b32_e32 v1, v10, v1 172; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 173; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 174; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 175; GFX10-NEXT: s_waitcnt vmcnt(0) 176; GFX10-NEXT: ; return to shader part epilog 177main_body: 178 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 179 ret <4 x float> %v 180} 181 182define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) { 183; GFX10-LABEL: sample_cd_cl_1d: 184; GFX10: ; %bb.0: ; %main_body 185; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 186; GFX10-NEXT: s_waitcnt vmcnt(0) 187; GFX10-NEXT: ; return to shader part epilog 188main_body: 189 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 190 ret <4 x float> %v 191} 192 193define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 194; GFX10-LABEL: sample_cd_cl_2d: 195; GFX10: ; %bb.0: ; %main_body 196; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff 197; GFX10-NEXT: v_and_b32_e32 v2, v7, v2 198; GFX10-NEXT: v_and_b32_e32 v0, v7, v0 199; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 200; GFX10-NEXT: v_lshl_or_b32 v3, v1, 16, v0 201; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v3, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 202; GFX10-NEXT: s_waitcnt vmcnt(0) 203; GFX10-NEXT: ; return to shader part epilog 204main_body: 205 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 206 ret <4 x float> %v 207} 208 209define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) { 210; GFX10-LABEL: sample_c_cd_cl_1d: 211; GFX10: ; %bb.0: ; %main_body 212; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 213; GFX10-NEXT: s_waitcnt vmcnt(0) 214; GFX10-NEXT: ; return to shader part epilog 215main_body: 216 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 217 ret <4 x float> %v 218} 219 220define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 221; GFX10-LABEL: sample_c_cd_cl_2d: 222; GFX10: ; %bb.0: ; %main_body 223; GFX10-NEXT: v_mov_b32_e32 v8, 0xffff 224; GFX10-NEXT: v_and_b32_e32 v3, v8, v3 225; GFX10-NEXT: v_and_b32_e32 v1, v8, v1 226; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 227; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 228; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 229; GFX10-NEXT: s_waitcnt vmcnt(0) 230; GFX10-NEXT: ; return to shader part epilog 231main_body: 232 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 233 ret <4 x float> %v 234} 235 236define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) { 237; GFX10-LABEL: sample_c_d_o_2darray_V1: 238; GFX10: ; %bb.0: ; %main_body 239; GFX10-NEXT: v_mov_b32_e32 v9, 0xffff 240; GFX10-NEXT: v_and_b32_e32 v4, v9, v4 241; GFX10-NEXT: v_and_b32_e32 v2, v9, v2 242; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4 243; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 244; GFX10-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v6, v7, v8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY 245; GFX10-NEXT: s_waitcnt vmcnt(0) 246; GFX10-NEXT: ; return to shader part epilog 247main_body: 248 %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 249 ret float %v 250} 251 252define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) { 253; GFX10-LABEL: sample_c_d_o_2darray_V2: 254; GFX10: ; %bb.0: ; %main_body 255; GFX10-NEXT: v_mov_b32_e32 v9, 0xffff 256; GFX10-NEXT: v_and_b32_e32 v4, v9, v4 257; GFX10-NEXT: v_and_b32_e32 v2, v9, v2 258; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4 259; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 260; GFX10-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v6, v7, v8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY 261; GFX10-NEXT: s_waitcnt vmcnt(0) 262; GFX10-NEXT: ; return to shader part epilog 263main_body: 264 %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 265 ret <2 x float> %v 266} 267 268declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 269declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 270declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 271declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 272declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 273declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 274declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 275declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 276declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 277 278declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 279declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 280declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 281declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 282declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 283declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 284declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 285declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 286 287declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 288declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 289 290attributes #0 = { nounwind } 291attributes #1 = { nounwind readonly } 292attributes #2 = { nounwind readnone } 293