1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
2
3; CHECK-LABEL: {{^}}test1:
4; CHECK: s_mov_b64 s[0:1], exec
5; CHECK: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
6;
7; Note: The hardware doesn't implement EXEC as src2 for v_cndmask.
8;
9; Note: We could generate better code here if we recognized earlier that
10; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However,
11; the expectation is that the intrinsic will be used in non-trivial shaders,
12; so such an optimization doesn't seem worth the effort.
13define amdgpu_ps float @test1() #0 {
14  %live = call i1 @llvm.amdgcn.ps.live()
15  %live.32 = zext i1 %live to i32
16  %r = bitcast i32 %live.32 to float
17  ret float %r
18}
19
20; CHECK-LABEL: {{^}}test2:
21; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
22; Following copy should go away:
23; CHECK: s_mov_b64 [[COPY:s\[[0-9]+:[0-9]+\]]], [[LIVE]]
24; CHECK-DAG: s_wqm_b64 exec, exec
25; CHECK-DAG: v_cndmask_b32_e64 [[VAR:v[0-9]+]], 0, 1, [[COPY]]
26; CHECK: image_sample v0, [[VAR]],
27define amdgpu_ps float @test2() #0 {
28  %live = call i1 @llvm.amdgcn.ps.live()
29  %live.32 = zext i1 %live to i32
30  %live.32.bc = bitcast i32 %live.32 to float
31  %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
32  %r = extractelement <4 x float> %t, i32 0
33  ret float %r
34}
35
36; CHECK-LABEL: {{^}}test3:
37; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
38; CHECK-DAG: s_wqm_b64 exec, exec
39; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1
40; CHECK_DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]]
41; CHECK: ; %dead
42define amdgpu_ps float @test3(i32 %in) #0 {
43entry:
44  %live = call i1 @llvm.amdgcn.ps.live()
45  br i1 %live, label %end, label %dead
46
47dead:
48  %tc.dead = mul i32 %in, 2
49  br label %end
50
51end:
52  %tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ]
53  %tc.bc = bitcast i32 %tc to float
54  %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0
55  %r = extractelement <4 x float> %t, i32 0
56  ret float %r
57}
58
59declare i1 @llvm.amdgcn.ps.live() #1
60declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
61
62attributes #0 = { nounwind }
63attributes #1 = { nounwind readnone }
64attributes #2 = { nounwind readonly }
65