1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=SICI,PREGFX10 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=VI,PREGFX10 3;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10 4 5;CHECK-LABEL: {{^}}buffer_load: 6;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}} 7;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}} 8;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}} 9;CHECK: s_waitcnt 10define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { 11main_body: 12 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0) 13 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1) 14 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2) 15 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 16 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 17 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 18 ret {<4 x float>, <4 x float>, <4 x float>} %r2 19} 20 21;CHECK-LABEL: {{^}}buffer_load_dlc: 22;PREGFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}} 23;PREGFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}} 24;PREGFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}} 25;GFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc{{$}} 26;GFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc{{$}} 27;GFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc{{$}} 28;CHECK: s_waitcnt 29define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) { 30main_body: 31 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4) 32 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5) 33 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6) 34 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 35 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 36 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 37 ret {<4 x float>, <4 x float>, <4 x float>} %r2 38} 39 40;CHECK-LABEL: {{^}}buffer_load_immoffs: 41;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40 42;CHECK: s_waitcnt 43define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { 44main_body: 45 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 40, i32 0, i32 0) 46 ret <4 x float> %data 47} 48 49;CHECK-LABEL: {{^}}buffer_load_immoffs_large: 50;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc 51;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:4 52;CHECK: s_waitcnt 53define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { 54main_body: 55 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 4, i32 8188, i32 0) 56 ret <4 x float> %data 57} 58 59;CHECK-LABEL: {{^}}buffer_load_ofs: 60;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen 61;CHECK: s_waitcnt 62define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { 63main_body: 64 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0) 65 ret <4 x float> %data 66} 67 68;CHECK-LABEL: {{^}}buffer_load_ofs_imm: 69;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60 70;CHECK: s_waitcnt 71define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { 72main_body: 73 %ofs = add i32 %1, 60 74 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0) 75 ret <4 x float> %data 76} 77 78;CHECK-LABEL: {{^}}buffer_load_x1: 79;CHECK: buffer_load_dword v0, v0, s[0:3], 0 offen 80;CHECK: s_waitcnt 81define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %ofs) { 82main_body: 83 %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0) 84 ret float %data 85} 86 87;CHECK-LABEL: {{^}}buffer_load_x2: 88;CHECK: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen 89;CHECK: s_waitcnt 90define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %ofs) { 91main_body: 92 %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0) 93 ret <2 x float> %data 94} 95 96;CHECK-LABEL: {{^}}buffer_load_negative_offset: 97;PREGFX10: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0 98;GFX10: v_add_nc_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], -16, v0 99;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen 100define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) { 101main_body: 102 %ofs.1 = add i32 %ofs, -16 103 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs.1, i32 0, i32 0) 104 ret <4 x float> %data 105} 106 107; SI won't merge ds memory operations, because of the signed offset bug, so 108; we only have check lines for VI. 109; CHECK-LABEL: buffer_load_mmo: 110; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 111; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4 112define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) { 113entry: 114 store float 0.0, float addrspace(3)* %lds 115 %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 116 %tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4 117 store float 0.0, float addrspace(3)* %tmp2 118 ret float %val 119} 120 121;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and: 122;CHECK-NEXT: %bb. 123;GFX10-NEXT: s_clause 124;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 125;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 126;CHECK: s_waitcnt 127define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) { 128main_body: 129 %a1 = add i32 %a, 4 130 %a2 = add i32 %a, 8 131 %a3 = add i32 %a, 12 132 %a4 = add i32 %a, 16 133 %a5 = add i32 %a, 28 134 %a6 = add i32 %a, 32 135 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 136 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 137 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0) 138 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0) 139 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) 140 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) 141 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 142 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 143 ret void 144} 145 146;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or: 147;CHECK-NEXT: %bb. 148;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0 149;GFX10-NEXT: s_clause 150;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4 151;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28 152;CHECK: s_waitcnt 153define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) { 154main_body: 155 %a = shl i32 %inp, 6 156 %a1 = or i32 %a, 4 157 %a2 = or i32 %a, 8 158 %a3 = or i32 %a, 12 159 %a4 = or i32 %a, 16 160 %a5 = or i32 %a, 28 161 %a6 = or i32 %a, 32 162 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 163 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 164 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0) 165 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0) 166 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) 167 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) 168 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 169 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 170 ret void 171} 172 173;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc: 174;CHECK-NEXT: %bb. 175;GFX10-NEXT: s_clause 176;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}} 177;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}} 178;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}} 179;CHECK: s_waitcnt 180define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) { 181main_body: 182 %a1 = add i32 %a, 4 183 %a2 = add i32 %a, 8 184 %a3 = add i32 %a, 12 185 %a4 = add i32 %a, 16 186 %a5 = add i32 %a, 28 187 %a6 = add i32 %a, 32 188 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 189 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 190 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 1) 191 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 1) 192 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 3) 193 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 3) 194 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 195 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 196 ret void 197} 198 199;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_and: 200;CHECK-NEXT: %bb. 201;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 202;CHECK: s_waitcnt 203define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) { 204main_body: 205 %a1 = add i32 %a, 4 206 %a2 = add i32 %a, 12 207 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 208 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 209 %r1 = extractelement <2 x float> %vr1, i32 0 210 %r2 = extractelement <2 x float> %vr1, i32 1 211 %r3 = extractelement <2 x float> %vr2, i32 0 212 %r4 = extractelement <2 x float> %vr2, i32 1 213 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 214 ret void 215} 216 217;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_or: 218;CHECK-NEXT: %bb. 219;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 4, v0 220;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4 221;CHECK: s_waitcnt 222define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) { 223main_body: 224 %a = shl i32 %inp, 4 225 %a1 = add i32 %a, 4 226 %a2 = add i32 %a, 12 227 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 228 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 229 %r1 = extractelement <2 x float> %vr1, i32 0 230 %r2 = extractelement <2 x float> %vr1, i32 1 231 %r3 = extractelement <2 x float> %vr2, i32 0 232 %r4 = extractelement <2 x float> %vr2, i32 1 233 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 234 ret void 235} 236 237;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged: 238;CHECK-NEXT: %bb. 239;GFX10-NEXT: s_clause 240;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 241;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28 242;CHECK: s_waitcnt 243define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { 244main_body: 245 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) 246 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0) 247 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0) 248 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0) 249 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0) 250 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0) 251 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 252 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 253 ret void 254} 255 256;CHECK-LABEL: {{^}}buffer_load_x2_offset_merged: 257;CHECK-NEXT: %bb. 258;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 259;CHECK: s_waitcnt 260define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) { 261main_body: 262 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) 263 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0) 264 %r1 = extractelement <2 x float> %vr1, i32 0 265 %r2 = extractelement <2 x float> %vr1, i32 1 266 %r3 = extractelement <2 x float> %vr2, i32 0 267 %r4 = extractelement <2 x float> %vr2, i32 1 268 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 269 ret void 270} 271 272;CHECK-LABEL: {{^}}buffer_load_int: 273;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 274;CHECK: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc 275;CHECK: buffer_load_dword v6, off, s[0:3], 0 slc 276;CHECK: s_waitcnt 277define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) { 278main_body: 279 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0) 280 %data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1) 281 %data_slc = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 2) 282 %fdata = bitcast <4 x i32> %data to <4 x float> 283 %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float> 284 %fdata_slc = bitcast i32 %data_slc to float 285 %r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0 286 %r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1 287 %r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2 288 ret {<4 x float>, <2 x float>, float} %r2 289} 290 291;CHECK-LABEL: {{^}}raw_buffer_load_ubyte: 292;CHECK-NEXT: %bb. 293;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 294;CHECK: s_waitcnt vmcnt(0) 295;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 296;CHECK-NEXT: ; return to shader part epilog 297define amdgpu_ps float @raw_buffer_load_ubyte(<4 x i32> inreg %rsrc) { 298main_body: 299 %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 300 %tmp2 = zext i8 %tmp to i32 301 %val = uitofp i32 %tmp2 to float 302 ret float %val 303} 304 305;CHECK-LABEL: {{^}}raw_buffer_load_i16: 306;CHECK-NEXT: %bb. 307;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 308;CHECK: s_waitcnt vmcnt(0) 309;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0 310;CHECK-NEXT: ; return to shader part epilog 311define amdgpu_ps float @raw_buffer_load_i16(<4 x i32> inreg %rsrc) { 312main_body: 313 %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 314 %tmp2 = zext i16 %tmp to i32 315 %val = uitofp i32 %tmp2 to float 316 ret float %val 317} 318 319;CHECK-LABEL: {{^}}raw_buffer_load_sbyte: 320;CHECK-NEXT: %bb. 321;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 322;CHECK: s_waitcnt vmcnt(0) 323;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 324;CHECK-NEXT: ; return to shader part epilog 325define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) { 326main_body: 327 %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 328 %tmp2 = sext i8 %tmp to i32 329 %val = sitofp i32 %tmp2 to float 330 ret float %val 331} 332 333;CHECK-LABEL: {{^}}raw_buffer_load_sshort: 334;CHECK-NEXT: %bb. 335;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 336;CHECK: s_waitcnt vmcnt(0) 337;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 338;CHECK-NEXT: ; return to shader part epilog 339define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) { 340main_body: 341 %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 342 %tmp2 = sext i16 %tmp to i32 343 %val = sitofp i32 %tmp2 to float 344 ret float %val 345} 346 347;CHECK-LABEL: {{^}}raw_buffer_load_f16: 348;CHECK-NEXT: %bb. 349;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], off, s[0:3], 0 350;CHECK: s_waitcnt vmcnt(0) 351;CHECK: ds_write_b16 v0, [[VAL]] 352define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, half addrspace(3)* %ptr) { 353main_body: 354 %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 355 store half %val, half addrspace(3)* %ptr 356 ret void 357} 358 359;CHECK-LABEL: {{^}}raw_buffer_load_v2f16: 360;CHECK-NEXT: %bb. 361;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], off, s[0:3], 0 362;CHECK: s_waitcnt vmcnt(0) 363;CHECK: ds_write_b32 v0, [[VAL]] 364define amdgpu_ps void @raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, <2 x half> addrspace(3)* %ptr) { 365main_body: 366 %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 367 store <2 x half> %val, <2 x half> addrspace(3)* %ptr 368 ret void 369} 370 371;CHECK-LABEL: {{^}}raw_buffer_load_v4f16: 372;CHECK-NEXT: %bb. 373;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0 374;CHECK: s_waitcnt vmcnt(0) 375;CHECK: ds_write_b64 v0, [[VAL]] 376define amdgpu_ps void @raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, <4 x half> addrspace(3)* %ptr) { 377main_body: 378 %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 379 store <4 x half> %val, <4 x half> addrspace(3)* %ptr 380 ret void 381} 382 383;CHECK-LABEL: {{^}}raw_buffer_load_v2i16: 384;CHECK-NEXT: %bb. 385;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], off, s[0:3], 0 386;CHECK: s_waitcnt vmcnt(0) 387;CHECK: ds_write_b32 v0, [[VAL]] 388define amdgpu_ps void @raw_buffer_load_v2i16(<4 x i32> inreg %rsrc, <2 x i16> addrspace(3)* %ptr) { 389main_body: 390 %val = call <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 391 store <2 x i16> %val, <2 x i16> addrspace(3)* %ptr 392 ret void 393} 394 395;CHECK-LABEL: {{^}}raw_buffer_load_v4i16: 396;CHECK-NEXT: %bb. 397;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0 398;CHECK: s_waitcnt vmcnt(0) 399;CHECK: ds_write_b64 v0, [[VAL]] 400define amdgpu_ps void @raw_buffer_load_v4i16(<4 x i32> inreg %rsrc, <4 x i16> addrspace(3)* %ptr) { 401main_body: 402 %val = call <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 403 store <4 x i16> %val, <4 x i16> addrspace(3)* %ptr 404 ret void 405} 406 407;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_merged: 408;CHECK-NEXT: %bb. 409;GFX10-NEXT: s_clause 410;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 411;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28 412;CHECK: s_waitcnt 413define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { 414main_body: 415 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) 416 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0) 417 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0) 418 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0) 419 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0) 420 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0) 421 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 422 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 423 ret void 424} 425 426;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_swizzled_not_merged: 427;CHECK-NEXT: %bb. 428;GFX10-NEXT: s_clause 429;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:4 430;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:8 431;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:12 432;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:16 433;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:28 434;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:32 435;CHECK: s_waitcnt 436define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc) { 437main_body: 438 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 8) 439 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 8) 440 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 8) 441 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 8) 442 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 8) 443 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 8) 444 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 445 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 446 ret void 447} 448 449declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) #0 450declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) #0 451declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #0 452declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #0 453declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32) #0 454declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32) #0 455declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 456declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32) #0 457declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32) #0 458declare <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32>, i32, i32, i32) #0 459declare <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32>, i32, i32, i32) #0 460declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #0 461declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #0 462declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #0 463 464attributes #0 = { nounwind readonly } 465