1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
2
3declare i32 @llvm.amdgcn.readlane(i32, i32) #0
4
5; CHECK-LABEL: {{^}}test_readlane_sreg_sreg:
6; CHECK-NOT: v_readlane_b32
7define amdgpu_kernel void @test_readlane_sreg_sreg(i32 %src0, i32 %src1) #1 {
8  %readlane = call i32 @llvm.amdgcn.readlane(i32 %src0, i32 %src1)
9  call void asm sideeffect "; use $0", "s"(i32 %readlane)
10  ret void
11}
12
13; CHECK-LABEL: {{^}}test_readlane_vreg_sreg:
14; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
15define amdgpu_kernel void @test_readlane_vreg_sreg(i32 %src0, i32 %src1) #1 {
16  %vgpr = call i32 asm sideeffect "; def $0", "=v"()
17  %readlane = call i32 @llvm.amdgcn.readlane(i32 %vgpr, i32 %src1)
18  call void asm sideeffect "; use $0", "s"(i32 %readlane)
19  ret void
20}
21
22; CHECK-LABEL: {{^}}test_readlane_imm_sreg:
23; CHECK-NOT: v_readlane_b32
24define amdgpu_kernel void @test_readlane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
25  %readlane = call i32 @llvm.amdgcn.readlane(i32 32, i32 %src1)
26  store i32 %readlane, i32 addrspace(1)* %out, align 4
27  ret void
28}
29
30; CHECK-LABEL: {{^}}test_readlane_vregs:
31; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
32; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, [[LANE]]
33define amdgpu_kernel void @test_readlane_vregs(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
34  %tid = call i32 @llvm.amdgcn.workitem.id.x()
35  %gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
36  %args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
37  %value = extractelement <2 x i32> %args, i32 0
38  %lane = extractelement <2 x i32> %args, i32 1
39  %readlane = call i32 @llvm.amdgcn.readlane(i32 %value, i32 %lane)
40  store i32 %readlane, i32 addrspace(1)* %out, align 4
41  ret void
42}
43
44; TODO: m0 should be folded.
45; CHECK-LABEL: {{^}}test_readlane_m0_sreg:
46; CHECK: s_mov_b32 m0, -1
47; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
48; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
49define amdgpu_kernel void @test_readlane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
50  %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
51  %readlane = call i32 @llvm.amdgcn.readlane(i32 %m0, i32 %src1)
52  store i32 %readlane, i32 addrspace(1)* %out, align 4
53  ret void
54}
55
56; CHECK-LABEL: {{^}}test_readlane_vgpr_imm:
57; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 32
58define amdgpu_kernel void @test_readlane_vgpr_imm(i32 addrspace(1)* %out) #1 {
59  %vgpr = call i32 asm sideeffect "; def $0", "=v"()
60  %readlane = call i32 @llvm.amdgcn.readlane(i32 %vgpr, i32 32) #0
61  store i32 %readlane, i32 addrspace(1)* %out, align 4
62  ret void
63}
64
65; CHECK-LABEL: {{^}}test_readlane_copy_from_sgpr:
66; CHECK: ;;#ASMSTART
67; CHECK-NEXT: s_mov_b32 [[SGPR:s[0-9]+]]
68; CHECK: ;;#ASMEND
69; CHECK-NOT: [[SGPR]]
70; CHECK-NOT: readlane
71; CHECK: v_mov_b32_e32 [[VCOPY:v[0-9]+]], [[SGPR]]
72; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VCOPY]]
73define amdgpu_kernel void @test_readlane_copy_from_sgpr(i32 addrspace(1)* %out) #1 {
74  %sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
75  %readfirstlane = call i32 @llvm.amdgcn.readlane(i32 %sgpr, i32 7)
76  store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
77  ret void
78}
79
80declare i32 @llvm.amdgcn.workitem.id.x() #2
81
82attributes #0 = { nounwind readnone convergent }
83attributes #1 = { nounwind }
84attributes #2 = { nounwind readnone }
85