1; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE64  %s
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE32 %s
3
4;CHECK-LABEL: {{^}}ret:
5;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
6;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
7;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]]
8;CHECK: v_cndmask_b32_e64 v0, 0, 1.0, [[WQM]]
9define amdgpu_ps float @ret(i32 %v0, i32 %v1) #1 {
10main_body:
11  %c = icmp eq i32 %v0, %v1
12  %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
13  %r = select i1 %w, float 1.0, float 0.0
14  ret float %r
15}
16
17;CHECK-LABEL: {{^}}true:
18;WAVE64: s_wqm_b64
19;WAVE32: s_wqm_b32
20define amdgpu_ps float @true() #1 {
21main_body:
22  %w = call i1 @llvm.amdgcn.wqm.vote(i1 true)
23  %r = select i1 %w, float 1.0, float 0.0
24  ret float %r
25}
26
27;CHECK-LABEL: {{^}}false:
28;WAVE64: s_wqm_b64
29;WAVE32: s_wqm_b32
30define amdgpu_ps float @false() #1 {
31main_body:
32  %w = call i1 @llvm.amdgcn.wqm.vote(i1 false)
33  %r = select i1 %w, float 1.0, float 0.0
34  ret float %r
35}
36
37;CHECK-LABEL: {{^}}kill:
38;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
39
40;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
41;WAVE64: s_and_b64 exec, exec, [[WQM]]
42
43;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]]
44;WAVE32: s_and_b32 exec_lo, exec_lo, [[WQM]]
45
46;CHECK: s_endpgm
47define amdgpu_ps void @kill(i32 %v0, i32 %v1) #1 {
48main_body:
49  %c = icmp eq i32 %v0, %v1
50  %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
51  call void @llvm.amdgcn.kill(i1 %w)
52  ret void
53}
54
55declare void @llvm.amdgcn.kill(i1) #1
56declare i1 @llvm.amdgcn.wqm.vote(i1)
57
58attributes #1 = { nounwind }
59