1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CI,CIGFX9 %s
2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,GFX9,CIGFX9 %s
3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
4
5declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #0
6
7; CHECK-LABEL: {{^}}test_writelane_sreg:
8; CIGFX9: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, m0
9; GFX10: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
10define amdgpu_kernel void @test_writelane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
11  %oldval = load i32, i32 addrspace(1)* %out
12  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
13  store i32 %writelane, i32 addrspace(1)* %out, align 4
14  ret void
15}
16
17; CHECK-LABEL: {{^}}test_writelane_imm_sreg:
18; CHECK: v_writelane_b32 v{{[0-9]+}}, 32, s{{[0-9]+}}
19define amdgpu_kernel void @test_writelane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
20  %oldval = load i32, i32 addrspace(1)* %out
21  %writelane = call i32 @llvm.amdgcn.writelane(i32 32, i32 %src1, i32 %oldval)
22  store i32 %writelane, i32 addrspace(1)* %out, align 4
23  ret void
24}
25
26; CHECK-LABEL: {{^}}test_writelane_vreg_lane:
27; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
28; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
29define amdgpu_kernel void @test_writelane_vreg_lane(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
30  %tid = call i32 @llvm.amdgcn.workitem.id.x()
31  %gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
32  %args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
33  %oldval = load i32, i32 addrspace(1)* %out
34  %lane = extractelement <2 x i32> %args, i32 1
35  %writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)
36  store i32 %writelane, i32 addrspace(1)* %out, align 4
37  ret void
38}
39
40; CHECK-LABEL: {{^}}test_writelane_m0_sreg:
41; CHECK: s_mov_b32 m0, -1
42; CIGFX9: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
43; CIGFX9: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], m0
44; GFX10: v_writelane_b32 v{{[0-9]+}}, m0, s{{[0-9]+}}
45define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
46  %oldval = load i32, i32 addrspace(1)* %out
47  %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
48  %writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)
49  store i32 %writelane, i32 addrspace(1)* %out, align 4
50  ret void
51}
52
53; CHECK-LABEL: {{^}}test_writelane_imm:
54; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 32
55define amdgpu_kernel void @test_writelane_imm(i32 addrspace(1)* %out, i32 %src0) #1 {
56  %oldval = load i32, i32 addrspace(1)* %out
57  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 32, i32 %oldval) #0
58  store i32 %writelane, i32 addrspace(1)* %out, align 4
59  ret void
60}
61
62; CHECK-LABEL: {{^}}test_writelane_sreg_oldval:
63; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], s{{[0-9]+}}
64; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
65; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
66define amdgpu_kernel void @test_writelane_sreg_oldval(i32 inreg %oldval, i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
67  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
68  store i32 %writelane, i32 addrspace(1)* %out, align 4
69  ret void
70}
71
72; CHECK-LABEL: {{^}}test_writelane_imm_oldval:
73; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], 42
74; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
75; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
76define amdgpu_kernel void @test_writelane_imm_oldval(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
77  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 42)
78  store i32 %writelane, i32 addrspace(1)* %out, align 4
79  ret void
80}
81
82declare i32 @llvm.amdgcn.workitem.id.x() #2
83
84attributes #0 = { nounwind readnone convergent }
85attributes #1 = { nounwind }
86attributes #2 = { nounwind readnone }
87