1;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=EG --check-prefix=FUNC 2;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CM --check-prefix=FUNC 3;RUN: llc < %s -march=amdgcn | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=SI --check-prefix=FUNC 4;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=SI --check-prefix=FUNC 5 6;FUNC-LABEL: {{^}}test: 7;EG: EXP_IEEE 8;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 9;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 10;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 11;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 12;SI: v_exp_f32 13 14define amdgpu_kernel void @test(float addrspace(1)* %out, float %in) { 15entry: 16 %0 = call float @llvm.exp2.f32(float %in) 17 store float %0, float addrspace(1)* %out 18 ret void 19} 20 21;FUNC-LABEL: {{^}}testv2: 22;EG: EXP_IEEE 23;EG: EXP_IEEE 24; FIXME: We should be able to merge these packets together on Cayman so we 25; have a maximum of 4 instructions. 26;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 27;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 28;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 29;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 30;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 31;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 32;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 33;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 34;SI: v_exp_f32 35;SI: v_exp_f32 36 37define amdgpu_kernel void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { 38entry: 39 %0 = call <2 x float> @llvm.exp2.v2f32(<2 x float> %in) 40 store <2 x float> %0, <2 x float> addrspace(1)* %out 41 ret void 42} 43 44;FUNC-LABEL: {{^}}testv4: 45;EG: EXP_IEEE 46;EG: EXP_IEEE 47;EG: EXP_IEEE 48;EG: EXP_IEEE 49; FIXME: We should be able to merge these packets together on Cayman so we 50; have a maximum of 4 instructions. 51;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 52;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 53;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 54;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 55;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 56;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 57;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 58;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 59;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 60;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 61;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 62;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 63;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 64;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 65;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 66;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} 67;SI: v_exp_f32 68;SI: v_exp_f32 69;SI: v_exp_f32 70;SI: v_exp_f32 71define amdgpu_kernel void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { 72entry: 73 %0 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %in) 74 store <4 x float> %0, <4 x float> addrspace(1)* %out 75 ret void 76} 77 78declare float @llvm.exp2.f32(float) readnone 79declare <2 x float> @llvm.exp2.v2f32(<2 x float>) readnone 80declare <4 x float> @llvm.exp2.v4f32(<4 x float>) readnone 81