1; RUN: llc -march=amdgcn < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s 4; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CM -check-prefix=FUNC %s 5 6; FUNC-LABEL: {{^}}test: 7; EG: LOG_IEEE 8; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 9; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 10; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 11; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 12; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 13; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}} 14define void @test(float addrspace(1)* %out, float %in) { 15entry: 16 %res = call float @llvm.log10.f32(float %in) 17 store float %res, float addrspace(1)* %out 18 ret void 19} 20 21; FUNC-LABEL: {{^}}testv2: 22; EG: LOG_IEEE 23; EG: LOG_IEEE 24; FIXME: We should be able to merge these packets together on Cayman so we 25; have a maximum of 4 instructions. 26; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 27; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 28; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 29; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 30; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 31; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 32; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 33; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 34; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 35; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3e9a209a 36; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 37; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}} 38; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}} 39define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { 40entry: 41 %res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in) 42 store <2 x float> %res, <2 x float> addrspace(1)* %out 43 ret void 44} 45 46; FUNC-LABEL: {{^}}testv4: 47; EG: LOG_IEEE 48; EG: LOG_IEEE 49; EG: LOG_IEEE 50; EG: LOG_IEEE 51; FIXME: We should be able to merge these packets together on Cayman so we 52; have a maximum of 4 instructions. 53; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 54; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 55; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 56; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 57; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 58; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 59; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 60; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 61; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 62; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 63; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 64; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 65; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 66; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 67; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 68; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} 69; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 70; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3e9a209a 71; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 72; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 73; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 74; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}} 75; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}} 76; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}} 77; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}} 78define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { 79entry: 80 %res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in) 81 store <4 x float> %res, <4 x float> addrspace(1)* %out 82 ret void 83} 84 85declare float @llvm.log10.f32(float) readnone 86declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone 87declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone 88