1; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
2
3; In moveToVALU(), move to vector ALU is performed, all instrs in
4; the use chain will be visited. We do not want the same node to be
5; pushed to the visit worklist more than once.
6
7; GCN-LABEL: {{^}}in_worklist_once:
8; GCN: buffer_load_dword
9; GCN: BB0_1:
10; GCN: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
11; GCN-NEXT: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
12; GCN: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
13; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
14define amdgpu_kernel void @in_worklist_once() #0 {
15bb:
16	%tmp = load i64, i64 addrspace(5)* undef
17br label %bb1
18
19bb1:                                              ; preds = %bb1, %bb
20	%tmp2 = phi i64 [ undef, %bb ], [ %tmp16, %bb1 ]
21	%tmp3 = phi i64 [ %tmp, %bb ], [ undef, %bb1 ]
22	%tmp11 = shl i64 %tmp2, 14
23	%tmp13 = xor i64 %tmp11, %tmp2
24	%tmp15 = and i64 %tmp3, %tmp13
25	%tmp16 = xor i64 %tmp15, %tmp3
26br label %bb1
27}
28
29attributes #0 = { nounwind }
30