1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra,si-optimize-exec-masking-pre-ra -o - %s | FileCheck %s 3 4# FIXME: Second run of the pass is a workaround for a bug in 5# -run-pass. The verifier doesn't detect broken LiveIntervals, see bug 6# 46873 7 8 9# Cannot fold this without moving the def of %7 after the and. 10--- 11name: no_fold_andn2_select_condition_live_out_phi 12tracksRegLiveness: true 13body: | 14 ; CHECK-LABEL: name: no_fold_andn2_select_condition_live_out_phi 15 ; CHECK: bb.0: 16 ; CHECK: successors: %bb.2(0x80000000) 17 ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1 18 ; CHECK: undef %1.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 19 ; CHECK: S_BRANCH %bb.2 20 ; CHECK: bb.1: 21 ; CHECK: S_ENDPGM 0 22 ; CHECK: bb.2: 23 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 24 ; CHECK: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec 25 ; CHECK: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec 26 ; CHECK: %1.sub1:vreg_64 = COPY %1.sub0 27 ; CHECK: DS_WRITE_B64_gfx9 undef %3:vgpr_32, %1, 0, 0, implicit $exec :: (store 8, addrspace 3) 28 ; CHECK: ATOMIC_FENCE 4, 2 29 ; CHECK: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 30 ; CHECK: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc 31 ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc 32 ; CHECK: S_BRANCH %bb.2 33 bb.0: 34 successors: %bb.2 35 36 %7:sreg_64_xexec = S_MOV_B64 -1 37 undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 38 S_BRANCH %bb.2 39 40 bb.1: 41 S_ENDPGM 0 42 43 bb.2: 44 successors: %bb.1, %bb.2 45 46 %4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %7, implicit $exec 47 V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec 48 %5.sub1:vreg_64 = COPY %5.sub0 49 DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3) 50 ATOMIC_FENCE 4, 2 51 %7:sreg_64_xexec = S_MOV_B64 0 52 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc 53 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc 54 S_BRANCH %bb.2 55 56... 57 58# It's OK to fold this, since the phi def is after the andn2 insert point. 59--- 60name: fold_andn2_select_condition_live_out_phi_reorder 61tracksRegLiveness: true 62body: | 63 ; CHECK-LABEL: name: fold_andn2_select_condition_live_out_phi_reorder 64 ; CHECK: bb.0: 65 ; CHECK: successors: %bb.2(0x80000000) 66 ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1 67 ; CHECK: undef %1.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 68 ; CHECK: S_BRANCH %bb.2 69 ; CHECK: bb.1: 70 ; CHECK: S_ENDPGM 0 71 ; CHECK: bb.2: 72 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 73 ; CHECK: %1.sub1:vreg_64 = COPY %1.sub0 74 ; CHECK: DS_WRITE_B64_gfx9 undef %3:vgpr_32, %1, 0, 0, implicit $exec :: (store 8, addrspace 3) 75 ; CHECK: ATOMIC_FENCE 4, 2 76 ; CHECK: $vcc = S_ANDN2_B64 $exec, [[S_MOV_B64_]], implicit-def dead $scc 77 ; CHECK: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 78 ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc 79 ; CHECK: S_BRANCH %bb.2 80 bb.0: 81 successors: %bb.2 82 83 %7:sreg_64_xexec = S_MOV_B64 -1 84 undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 85 S_BRANCH %bb.2 86 87 bb.1: 88 S_ENDPGM 0 89 90 bb.2: 91 successors: %bb.1, %bb.2 92 93 %4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %7, implicit $exec 94 V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec 95 %5.sub1:vreg_64 = COPY %5.sub0 96 DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3) 97 ATOMIC_FENCE 4, 2 98 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc 99 %7:sreg_64_xexec = S_MOV_B64 0 100 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc 101 S_BRANCH %bb.2 102 103... 104 105--- 106name: no_fold_andn2_select_condition_live_out_phi_physreg 107tracksRegLiveness: true 108body: | 109 ; CHECK-LABEL: name: no_fold_andn2_select_condition_live_out_phi_physreg 110 ; CHECK: bb.0: 111 ; CHECK: successors: %bb.2(0x80000000) 112 ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 -1 113 ; CHECK: undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 114 ; CHECK: S_BRANCH %bb.2 115 ; CHECK: bb.1: 116 ; CHECK: S_ENDPGM 0 117 ; CHECK: bb.2: 118 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 119 ; CHECK: liveins: $sgpr4_sgpr5 120 ; CHECK: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec 121 ; CHECK: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec 122 ; CHECK: %0.sub1:vreg_64 = COPY %0.sub0 123 ; CHECK: DS_WRITE_B64_gfx9 undef %2:vgpr_32, %0, 0, 0, implicit $exec :: (store 8, addrspace 3) 124 ; CHECK: ATOMIC_FENCE 4, 2 125 ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 0 126 ; CHECK: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc 127 ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc 128 ; CHECK: S_BRANCH %bb.2 129 bb.0: 130 successors: %bb.2 131 132 $sgpr4_sgpr5 = S_MOV_B64 -1 133 undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 134 S_BRANCH %bb.2 135 136 bb.1: 137 S_ENDPGM 0 138 139 bb.2: 140 successors: %bb.1, %bb.2 141 liveins: $sgpr4_sgpr5 142 143 %4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec 144 V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec 145 %5.sub1:vreg_64 = COPY %5.sub0 146 DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3) 147 ATOMIC_FENCE 4, 2 148 $sgpr4_sgpr5 = S_MOV_B64 0 149 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc 150 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc 151 S_BRANCH %bb.2 152 153... 154 155--- 156name: fold_andn2_select_condition_live_out_phi_physreg_reorder 157tracksRegLiveness: true 158body: | 159 ; CHECK-LABEL: name: fold_andn2_select_condition_live_out_phi_physreg_reorder 160 ; CHECK: bb.0: 161 ; CHECK: successors: %bb.2(0x80000000) 162 ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 -1 163 ; CHECK: undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 164 ; CHECK: S_BRANCH %bb.2 165 ; CHECK: bb.1: 166 ; CHECK: S_ENDPGM 0 167 ; CHECK: bb.2: 168 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 169 ; CHECK: liveins: $sgpr4_sgpr5 170 ; CHECK: %0.sub1:vreg_64 = COPY %0.sub0 171 ; CHECK: DS_WRITE_B64_gfx9 undef %2:vgpr_32, %0, 0, 0, implicit $exec :: (store 8, addrspace 3) 172 ; CHECK: ATOMIC_FENCE 4, 2 173 ; CHECK: $vcc = S_ANDN2_B64 $exec, $sgpr4_sgpr5, implicit-def dead $scc 174 ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 0 175 ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc 176 ; CHECK: S_BRANCH %bb.2 177 bb.0: 178 successors: %bb.2 179 180 $sgpr4_sgpr5 = S_MOV_B64 -1 181 undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec 182 S_BRANCH %bb.2 183 184 bb.1: 185 S_ENDPGM 0 186 187 bb.2: 188 successors: %bb.1, %bb.2 189 liveins: $sgpr4_sgpr5 190 191 %4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec 192 V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec 193 %5.sub1:vreg_64 = COPY %5.sub0 194 DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3) 195 ATOMIC_FENCE 4, 2 196 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc 197 $sgpr4_sgpr5 = S_MOV_B64 0 198 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc 199 S_BRANCH %bb.2 200 201... 202