1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-flat-for-global -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s
2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s
4
5
6; GCN-LABEL: {{^}}s_pack_v2i16:
7; GFX9: s_load_dword [[VAL0:s[0-9]+]]
8; GFX9: s_load_dword [[VAL1:s[0-9]+]]
9; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
10; GFX9: ; use [[PACKED]]
11define amdgpu_kernel void @s_pack_v2i16(i32 addrspace(4)* %in0, i32 addrspace(4)* %in1) #0 {
12  %val0 = load volatile i32, i32 addrspace(4)* %in0
13  %val1 = load volatile i32, i32 addrspace(4)* %in1
14  %lo = trunc i32 %val0 to i16
15  %hi = trunc i32 %val1 to i16
16  %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
17  %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
18  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
19
20  call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
21  ret void
22}
23
24; GCN-LABEL: {{^}}s_pack_v2i16_imm_lo:
25; GFX9: s_load_dword [[VAL1:s[0-9]+]]
26; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1c8, [[VAL1]]
27; GFX9: ; use [[PACKED]]
28define amdgpu_kernel void @s_pack_v2i16_imm_lo(i32 addrspace(4)* %in1) #0 {
29  %val1 = load i32, i32 addrspace(4)* %in1
30  %hi = trunc i32 %val1 to i16
31  %vec.0 = insertelement <2 x i16> undef, i16 456, i32 0
32  %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
33  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
34
35  call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
36  ret void
37}
38
39; GCN-LABEL: {{^}}s_pack_v2i16_imm_hi:
40; GFX9: s_load_dword [[VAL0:s[0-9]+]]
41; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1c8
42; GFX9: ; use [[PACKED]]
43define amdgpu_kernel void @s_pack_v2i16_imm_hi(i32 addrspace(4)* %in0) #0 {
44  %val0 = load i32, i32 addrspace(4)* %in0
45  %lo = trunc i32 %val0 to i16
46  %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
47  %vec.1 = insertelement <2 x i16> %vec.0, i16 456, i32 1
48  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
49
50  call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
51  ret void
52}
53
54; GCN-LABEL: {{^}}v_pack_v2i16:
55; GFX9: global_load_dword [[VAL0:v[0-9]+]]
56; GFX9: global_load_dword [[VAL1:v[0-9]+]]
57
58; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
59; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[MASKED]]
60; GFX9: ; use [[PACKED]]
61define amdgpu_kernel void @v_pack_v2i16(i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #0 {
62  %tid = call i32 @llvm.amdgcn.workitem.id.x()
63  %tid.ext = sext i32 %tid to i64
64  %in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
65  %in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
66  %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
67  %val1 = load volatile i32, i32 addrspace(1)* %in1.gep
68  %lo = trunc i32 %val0 to i16
69  %hi = trunc i32 %val1 to i16
70  %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
71  %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
72  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
73  call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
74  ret void
75}
76
77; GCN-LABEL: {{^}}v_pack_v2i16_user:
78; GFX9: global_load_dword [[VAL0:v[0-9]+]]
79; GFX9: global_load_dword [[VAL1:v[0-9]+]]
80
81; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
82; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[MASKED]]
83
84; GFX9: v_add_u32_e32 v{{[0-9]+}}, 9, [[PACKED]]
85define amdgpu_kernel void @v_pack_v2i16_user(i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #0 {
86  %tid = call i32 @llvm.amdgcn.workitem.id.x()
87  %tid.ext = sext i32 %tid to i64
88  %in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
89  %in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
90  %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
91  %val1 = load volatile i32, i32 addrspace(1)* %in1.gep
92  %lo = trunc i32 %val0 to i16
93  %hi = trunc i32 %val1 to i16
94  %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
95  %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
96  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
97  %foo = add i32 %vec.i32, 9
98  store volatile i32 %foo, i32 addrspace(1)* undef
99  ret void
100}
101
102; GCN-LABEL: {{^}}v_pack_v2i16_imm_lo:
103; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]]
104; GFX9-DENORM-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7b{{$}}
105
106; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b{{$}}
107; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[K]]
108
109; GFX9: ; use [[PACKED]]
110define amdgpu_kernel void @v_pack_v2i16_imm_lo(i32 addrspace(1)* %in1) #0 {
111  %tid = call i32 @llvm.amdgcn.workitem.id.x()
112  %tid.ext = sext i32 %tid to i64
113  %in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
114  %val1 = load volatile i32, i32 addrspace(1)* %in1.gep
115  %hi = trunc i32 %val1 to i16
116  %vec.0 = insertelement <2 x i16> undef, i16 123, i32 0
117  %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
118  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
119  call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
120  ret void
121}
122
123; GCN-LABEL: {{^}}v_pack_v2i16_inline_imm_lo:
124; GFX9: global_load_dword [[VAL1:v[0-9]+]]
125
126; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, 64
127; GFX9: ; use [[PACKED]]
128define amdgpu_kernel void @v_pack_v2i16_inline_imm_lo(i32 addrspace(1)* %in1) #0 {
129  %tid = call i32 @llvm.amdgcn.workitem.id.x()
130  %tid.ext = sext i32 %tid to i64
131  %in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
132  %val1 = load volatile i32, i32 addrspace(1)* %in1.gep
133  %hi = trunc i32 %val1 to i16
134  %vec.0 = insertelement <2 x i16> undef, i16 64, i32 0
135  %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
136  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
137  call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
138  ret void
139}
140
141; GCN-LABEL: {{^}}v_pack_v2i16_imm_hi:
142; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]]
143
144; GFX9-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7b{{$}}
145; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[K]], 16, [[VAL0]]
146
147; GFX9: ; use [[PACKED]]
148define amdgpu_kernel void @v_pack_v2i16_imm_hi(i32 addrspace(1)* %in0) #0 {
149  %tid = call i32 @llvm.amdgcn.workitem.id.x()
150  %tid.ext = sext i32 %tid to i64
151  %in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
152  %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
153  %lo = trunc i32 %val0 to i16
154  %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
155  %vec.1 = insertelement <2 x i16> %vec.0, i16 123, i32 1
156  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
157  call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
158  ret void
159}
160
161; GCN-LABEL: {{^}}v_pack_v2i16_inline_imm_hi:
162; GFX9: global_load_dword [[VAL:v[0-9]+]]
163; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], 7, 16, [[VAL]]
164; GFX9: ; use [[PACKED]]
165define amdgpu_kernel void @v_pack_v2i16_inline_imm_hi(i32 addrspace(1)* %in0) #0 {
166  %tid = call i32 @llvm.amdgcn.workitem.id.x()
167  %tid.ext = sext i32 %tid to i64
168  %in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
169  %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
170  %lo = trunc i32 %val0 to i16
171  %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
172  %vec.1 = insertelement <2 x i16> %vec.0, i16 7, i32 1
173  %vec.i32 = bitcast <2 x i16> %vec.1 to i32
174  call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
175  ret void
176}
177
178declare i32 @llvm.amdgcn.workitem.id.x() #1
179
180attributes #0 = { nounwind }
181attributes #1 = { nounwind readnone }
182