1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
3
4; GCN-LABEL: {{^}}shl_i16:
5; GCN: v_lshlrev_b16_e{{32|64}} [[OP:v[0-9]+]],
6; GCN-NEXT: s_setpc_b64
7define i16 @shl_i16(i16 %x, i16 %y) {
8  %res = shl i16 %x, %y
9  ret i16 %res
10}
11
12; GCN-LABEL: {{^}}lshr_i16:
13; GCN: v_lshrrev_b16_e{{32|64}} [[OP:v[0-9]+]],
14; GCN-NEXT: s_setpc_b64
15define i16 @lshr_i16(i16 %x, i16 %y) {
16  %res = lshr i16 %x, %y
17  ret i16 %res
18}
19
20; GCN-LABEL: {{^}}ashr_i16:
21; GCN: v_ashrrev_i16_e{{32|64}} [[OP:v[0-9]+]],
22; GCN-NEXT: s_setpc_b64
23define i16 @ashr_i16(i16 %x, i16 %y) {
24  %res = ashr i16 %x, %y
25  ret i16 %res
26}
27
28; GCN-LABEL: {{^}}add_u16:
29; GCN: v_add_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
30; GCN-NEXT: s_setpc_b64
31define i16 @add_u16(i16 %x, i16 %y) {
32  %res = add i16 %x, %y
33  ret i16 %res
34}
35
36; GCN-LABEL: {{^}}sub_u16:
37; GCN: v_sub_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
38; GCN-NEXT: s_setpc_b64
39define i16 @sub_u16(i16 %x, i16 %y) {
40  %res = sub i16 %x, %y
41  ret i16 %res
42}
43
44; GCN-LABEL: {{^}}mul_lo_u16:
45; GCN: v_mul_lo_u16_e{{32|64}} [[OP:v[0-9]+]],
46; GCN-NEXT: s_setpc_b64
47define i16 @mul_lo_u16(i16 %x, i16 %y) {
48  %res = mul i16 %x, %y
49  ret i16 %res
50}
51
52; GCN-LABEL: {{^}}min_u16:
53; GCN: v_min_u16_e{{32|64}} [[OP:v[0-9]+]],
54; GCN-NEXT: s_setpc_b64
55define i16 @min_u16(i16 %x, i16 %y) {
56  %cmp = icmp ule i16 %x, %y
57  %res = select i1 %cmp, i16 %x, i16 %y
58  ret i16 %res
59}
60
61; GCN-LABEL: {{^}}min_i16:
62; GCN: v_min_i16_e{{32|64}} [[OP:v[0-9]+]],
63; GCN-NEXT: s_setpc_b64
64define i16 @min_i16(i16 %x, i16 %y) {
65  %cmp = icmp sle i16 %x, %y
66  %res = select i1 %cmp, i16 %x, i16 %y
67  ret i16 %res
68}
69
70; GCN-LABEL: {{^}}max_u16:
71; GCN: v_max_u16_e{{32|64}} [[OP:v[0-9]+]],
72; GCN-NEXT: s_setpc_b64
73define i16 @max_u16(i16 %x, i16 %y) {
74  %cmp = icmp uge i16 %x, %y
75  %res = select i1 %cmp, i16 %x, i16 %y
76  ret i16 %res
77}
78
79; GCN-LABEL: {{^}}max_i16:
80; GCN: v_max_i16_e{{32|64}} [[OP:v[0-9]+]],
81; GCN-NEXT: s_setpc_b64
82define i16 @max_i16(i16 %x, i16 %y) {
83  %cmp = icmp sge i16 %x, %y
84  %res = select i1 %cmp, i16 %x, i16 %y
85  ret i16 %res
86}
87
88; GCN-LABEL: {{^}}shl_i16_zext_i32:
89; GCN: v_lshlrev_b16_e{{32|64}} [[OP:v[0-9]+]],
90; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
91; GCN-NEXT: s_setpc_b64
92define i32 @shl_i16_zext_i32(i16 %x, i16 %y) {
93  %res = shl i16 %x, %y
94  %zext = zext i16 %res to i32
95  ret i32 %zext
96}
97
98; GCN-LABEL: {{^}}lshr_i16_zext_i32:
99; GCN: v_lshrrev_b16_e{{32|64}} [[OP:v[0-9]+]],
100; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
101; GCN-NEXT: s_setpc_b64
102define i32 @lshr_i16_zext_i32(i16 %x, i16 %y) {
103  %res = lshr i16 %x, %y
104  %zext = zext i16 %res to i32
105  ret i32 %zext
106}
107
108; GCN-LABEL: {{^}}ashr_i16_zext_i32:
109; GCN: v_ashrrev_i16_e{{32|64}} [[OP:v[0-9]+]],
110; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
111; GCN-NEXT: s_setpc_b64
112define i32 @ashr_i16_zext_i32(i16 %x, i16 %y) {
113  %res = ashr i16 %x, %y
114  %zext = zext i16 %res to i32
115  ret i32 %zext
116}
117
118; GCN-LABEL: {{^}}add_u16_zext_i32:
119; GCN: v_add_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
120; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
121; GCN-NEXT: s_setpc_b64
122define i32 @add_u16_zext_i32(i16 %x, i16 %y) {
123  %res = add i16 %x, %y
124  %zext = zext i16 %res to i32
125  ret i32 %zext
126}
127
128; GCN-LABEL: {{^}}sub_u16_zext_i32:
129; GCN: v_sub_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
130; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
131; GCN-NEXT: s_setpc_b64
132define i32 @sub_u16_zext_i32(i16 %x, i16 %y) {
133  %res = sub i16 %x, %y
134  %zext = zext i16 %res to i32
135  ret i32 %zext
136}
137
138; GCN-LABEL: {{^}}mul_lo_u16_zext_i32:
139; GCN: v_mul_lo_u16_e{{32|64}} [[OP:v[0-9]+]],
140; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
141; GCN-NEXT: s_setpc_b64
142define i32 @mul_lo_u16_zext_i32(i16 %x, i16 %y) {
143  %res = mul i16 %x, %y
144  %zext = zext i16 %res to i32
145  ret i32 %zext
146}
147
148; GCN-LABEL: {{^}}min_u16_zext_i32:
149; GCN: v_min_u16_e{{32|64}} [[OP:v[0-9]+]],
150; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
151; GCN-NEXT: s_setpc_b64
152define i32 @min_u16_zext_i32(i16 %x, i16 %y) {
153  %cmp = icmp ule i16 %x, %y
154  %res = select i1 %cmp, i16 %x, i16 %y
155  %zext = zext i16 %res to i32
156  ret i32 %zext
157}
158
159; GCN-LABEL: {{^}}min_i16_zext_i32:
160; GCN: v_min_i16_e{{32|64}} [[OP:v[0-9]+]],
161; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
162; GCN-NEXT: s_setpc_b64
163define i32 @min_i16_zext_i32(i16 %x, i16 %y) {
164  %cmp = icmp sle i16 %x, %y
165  %res = select i1 %cmp, i16 %x, i16 %y
166  %zext = zext i16 %res to i32
167  ret i32 %zext
168}
169
170; GCN-LABEL: {{^}}max_u16_zext_i32:
171; GCN: v_max_u16_e{{32|64}} [[OP:v[0-9]+]],
172; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
173; GCN-NEXT: s_setpc_b64
174define i32 @max_u16_zext_i32(i16 %x, i16 %y) {
175  %cmp = icmp uge i16 %x, %y
176  %res = select i1 %cmp, i16 %x, i16 %y
177  %zext = zext i16 %res to i32
178  ret i32 %zext
179}
180
181; GCN-LABEL: {{^}}max_i16_zext_i32:
182; GCN: v_max_i16_e{{32|64}} [[OP:v[0-9]+]],
183; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
184; GCN-NEXT: s_setpc_b64
185define i32 @max_i16_zext_i32(i16 %x, i16 %y) {
186  %cmp = icmp sge i16 %x, %y
187  %res = select i1 %cmp, i16 %x, i16 %y
188  %zext = zext i16 %res to i32
189  ret i32 %zext
190}
191