1# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -run-pass greedy,amdgpu-regbanks-reassign,virtregrewriter -o - %s | FileCheck -check-prefix=GCN %s
2
3
4# Test that subreg reassignments are correctly handled when whole register also
5# conflicts.  If this is mishandled stall counts will be incorrect and cause an
6# infinite loop.
7# GCN-LABEL: vgpr64_mixed_use{{$}}
8# GCN: $vgpr0_vgpr1 = IMPLICIT_DEF
9# GCN: $vgpr4_vgpr5 = IMPLICIT_DEF
10# GCN: $vcc = IMPLICIT_DEF
11# GCN: $vgpr2_vgpr3 = IMPLICIT_DEF
12# GCN: $vgpr6_vgpr7 = IMPLICIT_DEF
13# GCN: $vgpr8_vgpr9_vgpr10_vgpr11 = IMPLICIT_DEF
14# GCN: $vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF
15# GCN: $vgpr16_vgpr17_vgpr18_vgpr19 = IMPLICIT_DEF
16# GCN: $vgpr20_vgpr21_vgpr22_vgpr23 = IMPLICIT_DEF
17# GCN: $vgpr24_vgpr25_vgpr26_vgpr27 = IMPLICIT_DEF
18# GCN: $vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF
19# GCN: $vgpr32_vgpr33_vgpr34_vgpr35 = IMPLICIT_DEF
20# GCN: $vgpr36_vgpr37_vgpr38_vgpr39 = IMPLICIT_DEF
21# GCN: $vgpr40_vgpr41_vgpr42_vgpr43 = IMPLICIT_DEF
22# GCN: $vgpr44_vgpr45_vgpr46_vgpr47 = IMPLICIT_DEF
23# GCN: $vgpr2 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr5, $vcc, implicit $exec
24# GCN: $vgpr2 = V_CNDMASK_B32_e64 0, $vgpr0, 0, $vgpr4, killed $vcc, implicit $exec
25# GCN: $sgpr0_sgpr1 = V_CMP_LT_U64_e64 $vgpr4_vgpr5, $vgpr0_vgpr1, implicit $exec
26---
27name:            vgpr64_mixed_use
28tracksRegLiveness: true
29registers:
30  - { id: 0, class: vreg_64, preferred-register: '$vgpr0_vgpr1' }
31  - { id: 1, class: vreg_64, preferred-register: '$vgpr4_vgpr5' }
32  - { id: 2, class: sreg_64_xexec, preferred-register: '$vcc' }
33  - { id: 3, class: vgpr_32 }
34  - { id: 4, class: vgpr_32 }
35  - { id: 5, class: sreg_64_xexec }
36  - { id: 6, class: vreg_64, preferred-register: '$vgpr2_vgpr3' }
37  - { id: 7, class: vreg_64, preferred-register: '$vgpr6_vgpr7' }
38  - { id: 8, class: vreg_128, preferred-register: '$vgpr8_vgpr9_vgpr10_vgpr11' }
39  - { id: 9, class: vreg_128, preferred-register: '$vgpr12_vgpr13_vgpr14_vgpr15' }
40  - { id: 10, class: vreg_128, preferred-register: '$vgpr16_vgpr17_vgpr18_vgpr19' }
41  - { id: 11, class: vreg_128, preferred-register: '$vgpr20_vgpr21_vgpr22_vgpr23' }
42  - { id: 12, class: vreg_128, preferred-register: '$vgpr24_vgpr25_vgpr26_vgpr27' }
43  - { id: 13, class: vreg_128, preferred-register: '$vgpr28_vgpr29_vgpr30_vgpr31' }
44  - { id: 14, class: vreg_128, preferred-register: '$vgpr32_vgpr33_vgpr34_vgpr35' }
45  - { id: 15, class: vreg_128, preferred-register: '$vgpr36_vgpr37_vgpr38_vgpr39' }
46  - { id: 16, class: vreg_128, preferred-register: '$vgpr40_vgpr41_vgpr42_vgpr43' }
47  - { id: 17, class: vreg_128, preferred-register: '$vgpr44_vgpr45_vgpr46_vgpr47' }
48body: |
49  bb.0:
50    %0 = IMPLICIT_DEF
51    %1 = IMPLICIT_DEF
52    %2 = IMPLICIT_DEF
53    %6 = IMPLICIT_DEF
54    %7 = IMPLICIT_DEF
55    %8 = IMPLICIT_DEF
56    %9 = IMPLICIT_DEF
57    %10 = IMPLICIT_DEF
58    %11 = IMPLICIT_DEF
59    %12 = IMPLICIT_DEF
60    %13 = IMPLICIT_DEF
61    %14 = IMPLICIT_DEF
62    %15 = IMPLICIT_DEF
63    %16 = IMPLICIT_DEF
64    %17 = IMPLICIT_DEF
65    %3 = V_CNDMASK_B32_e64 0, %0.sub1, 0, %1.sub1, %2, implicit $exec
66    %4 = V_CNDMASK_B32_e64 0, %0.sub0, 0, %1.sub0, %2, implicit $exec
67    %5 = V_CMP_LT_U64_e64 %1, %0, implicit $exec
68    S_ENDPGM 0
69...
70