1# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s
2# REQUIRES: asserts
3#
4# This test will provoke a Couldn't join subrange unreachable without the
5# fix for http://llvm.org/PR35373
6#
7# GCN: S_CBRANCH_SCC1 %bb.6, implicit undef $scc
8
9--- |
10  define amdgpu_ps void @regcoal-subrange-join-seg() local_unnamed_addr #0 {
11    ret void
12  }
13...
14---
15name:            regcoal-subrange-join-seg
16tracksRegLiveness: true
17registers:
18  - { id: 0, class: sgpr_128 }
19  - { id: 1, class: sgpr_128 }
20  - { id: 2, class: sgpr_128 }
21  - { id: 3, class: sgpr_128 }
22  - { id: 4, class: sgpr_128 }
23  - { id: 5, class: sgpr_128 }
24  - { id: 6, class: sgpr_128 }
25  - { id: 7, class: sgpr_128 }
26  - { id: 8, class: sgpr_128 }
27  - { id: 9, class: sreg_32_xm0 }
28  - { id: 10, class: sreg_32_xm0 }
29  - { id: 11, class: vgpr_32 }
30  - { id: 12, class: vgpr_32 }
31  - { id: 13, class: vgpr_32 }
32  - { id: 14, class: sreg_32_xm0_xexec }
33  - { id: 15, class: sgpr_128 }
34  - { id: 16, class: sreg_32 }
35  - { id: 17, class: sreg_32_xm0 }
36  - { id: 18, class: sreg_32_xm0 }
37  - { id: 19, class: sreg_32_xm0 }
38  - { id: 20, class: sreg_32_xm0 }
39  - { id: 21, class: sreg_32_xm0_xexec }
40  - { id: 22, class: sgpr_128 }
41  - { id: 23, class: sreg_32_xm0 }
42  - { id: 24, class: vgpr_32 }
43  - { id: 25, class: sreg_64_xexec }
44  - { id: 26, class: vgpr_32 }
45  - { id: 27, class: sreg_32_xm0 }
46  - { id: 28, class: sreg_32 }
47  - { id: 29, class: sgpr_128 }
48  - { id: 30, class: sreg_32_xm0 }
49  - { id: 31, class: sreg_32_xm0 }
50  - { id: 32, class: vgpr_32 }
51  - { id: 33, class: vgpr_32 }
52  - { id: 34, class: vgpr_32 }
53  - { id: 35, class: vgpr_32 }
54  - { id: 36, class: vgpr_32 }
55  - { id: 37, class: vgpr_32 }
56  - { id: 38, class: vgpr_32 }
57  - { id: 39, class: vgpr_32 }
58  - { id: 40, class: vgpr_32 }
59  - { id: 41, class: vgpr_32 }
60  - { id: 42, class: vgpr_32 }
61  - { id: 43, class: vgpr_32 }
62  - { id: 44, class: vgpr_32 }
63  - { id: 45, class: vgpr_32 }
64  - { id: 46, class: vgpr_32 }
65  - { id: 47, class: vgpr_32 }
66  - { id: 48, class: vgpr_32 }
67  - { id: 49, class: vreg_128 }
68  - { id: 50, class: vreg_128 }
69  - { id: 51, class: vreg_128 }
70  - { id: 52, class: vreg_128 }
71  - { id: 53, class: vreg_128 }
72  - { id: 54, class: vreg_128 }
73  - { id: 55, class: vgpr_32 }
74  - { id: 56, class: vreg_128 }
75  - { id: 57, class: vreg_128 }
76  - { id: 58, class: vreg_128 }
77  - { id: 59, class: vreg_128 }
78  - { id: 60, class: vreg_128 }
79  - { id: 61, class: vreg_128 }
80  - { id: 62, class: vreg_128 }
81  - { id: 63, class: vreg_128 }
82body:             |
83  bb.0:
84    S_CBRANCH_SCC1 %bb.6, implicit undef $scc
85    S_BRANCH %bb.1
86
87  bb.1:
88    S_CBRANCH_SCC1 %bb.4, implicit undef $scc
89    S_BRANCH %bb.2
90
91  bb.2:
92    S_CBRANCH_SCC1 %bb.4, implicit undef $scc
93    S_BRANCH %bb.3
94
95  bb.3:
96
97  bb.4:
98    successors: %bb.5, %bb.6
99
100    S_CBRANCH_SCC1 %bb.6, implicit undef $scc
101    S_BRANCH %bb.5
102
103  bb.5:
104
105  bb.6:
106    S_CBRANCH_SCC1 %bb.14, implicit undef $scc
107    S_BRANCH %bb.7
108
109  bb.7:
110    S_CBRANCH_SCC1 %bb.9, implicit undef $scc
111    S_BRANCH %bb.8
112
113  bb.8:
114
115  bb.9:
116    successors: %bb.10, %bb.13
117
118    S_CBRANCH_SCC1 %bb.13, implicit undef $scc
119    S_BRANCH %bb.10
120
121  bb.10:
122    S_CBRANCH_SCC1 %bb.12, implicit undef $scc
123    S_BRANCH %bb.11
124
125  bb.11:
126
127  bb.12:
128
129  bb.13:
130
131  bb.14:
132    S_CBRANCH_SCC1 %bb.26, implicit undef $scc
133    S_BRANCH %bb.15
134
135  bb.15:
136    S_CBRANCH_SCC1 %bb.20, implicit undef $scc
137    S_BRANCH %bb.16
138
139  bb.16:
140    successors: %bb.17, %bb.19
141
142    S_CBRANCH_SCC1 %bb.19, implicit undef $scc
143    S_BRANCH %bb.17
144
145  bb.17:
146    successors: %bb.18, %bb.19
147
148    S_CBRANCH_SCC1 %bb.19, implicit undef $scc
149    S_BRANCH %bb.18
150
151  bb.18:
152
153  bb.19:
154
155  bb.20:
156    S_CBRANCH_SCC1 %bb.25, implicit undef $scc
157    S_BRANCH %bb.21
158
159  bb.21:
160    successors: %bb.22, %bb.24
161
162    S_CBRANCH_SCC1 %bb.24, implicit undef $scc
163    S_BRANCH %bb.22
164
165  bb.22:
166    successors: %bb.23, %bb.24
167
168    S_CBRANCH_SCC1 %bb.24, implicit undef $scc
169    S_BRANCH %bb.23
170
171  bb.23:
172
173  bb.24:
174
175  bb.25:
176
177  bb.26:
178    S_CBRANCH_SCC1 %bb.35, implicit undef $scc
179    S_BRANCH %bb.27
180
181  bb.27:
182    S_CBRANCH_SCC1 %bb.32, implicit undef $scc
183    S_BRANCH %bb.28
184
185  bb.28:
186    %9 = S_FF1_I32_B32 undef %10
187    %13 = V_MAD_U32_U24 killed %9, 48, 32, 0, implicit $exec
188    %45 = BUFFER_LOAD_DWORD_OFFEN killed %13, undef %15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
189    %46 = V_AND_B32_e32 1, killed %45, implicit $exec
190    %21 = S_BUFFER_LOAD_DWORD_SGPR undef %22, undef %23, 0, 0 :: (dereferenceable invariant load 4)
191    %25 = nofpexcept V_CMP_GE_F32_e64 0, 0, 0, killed %21, 0, implicit $mode, implicit $exec
192    %26 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %25, implicit $exec
193    %62 = IMPLICIT_DEF
194
195  bb.29:
196    successors: %bb.30(0x30000000), %bb.36(0x50000000)
197
198    %53 = COPY killed %62
199    %47 = V_ADD_CO_U32_e32 -1, %46, implicit-def dead $vcc, implicit $exec
200    %48 = V_OR_B32_e32 killed %47, %26, implicit $exec
201    %49 = COPY %53
202    %49.sub2 = COPY undef %48
203    %51 = COPY killed %49
204    %51.sub3 = COPY undef %26
205    V_CMP_NE_U32_e32 0, killed %48, implicit-def $vcc, implicit $exec
206    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
207    S_CBRANCH_VCCZ %bb.30, implicit killed $vcc
208
209  bb.36:
210    %63 = COPY killed %51
211    S_BRANCH %bb.31
212
213  bb.30:
214    %33 = nofpexcept V_MAD_F32 1, killed %53.sub0, 0, undef %34, 0, 0, 0, 0, implicit $mode, implicit $exec
215    %35 = nofpexcept V_MAC_F32_e32 killed %33, undef %36, undef %35, implicit $mode, implicit $exec
216    %38 = nofpexcept V_MAX_F32_e32 0, killed %35, implicit $mode, implicit $exec
217    %39 = nofpexcept V_LOG_F32_e32 killed %38, implicit $mode, implicit $exec
218    %40 = nofpexcept V_MUL_F32_e32 killed %39, undef %41, implicit $mode, implicit $exec
219    %42 = nofpexcept V_EXP_F32_e32 killed %40, implicit $mode, implicit $exec
220    dead %43 = nofpexcept V_MUL_F32_e32 killed %42, undef %44, implicit $mode, implicit $exec
221    %63 = COPY killed %51
222
223  bb.31:
224    %52 = COPY killed %63
225    %62 = COPY killed %52
226    S_BRANCH %bb.29
227
228  bb.32:
229    S_CBRANCH_SCC1 %bb.34, implicit undef $scc
230    S_BRANCH %bb.33
231
232  bb.33:
233
234  bb.34:
235
236  bb.35:
237    S_ENDPGM 0
238
239...
240