1; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -amdgpu-lower-kernel-attributes -instcombine %s | FileCheck -enable-var-scope %s 2 3target datalayout = "n32" 4 5; CHECK-LABEL: @invalid_reqd_work_group_size( 6; CHECK: load i16, 7define amdgpu_kernel void @invalid_reqd_work_group_size(i16 addrspace(1)* %out) #0 !reqd_work_group_size !1 { 8 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 9 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 10 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 11 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 12 store i16 %group.size.x, i16 addrspace(1)* %out 13 ret void 14} 15 16; CHECK-LABEL: @volatile_load_group_size_x( 17; CHECK: load volatile i16, 18define amdgpu_kernel void @volatile_load_group_size_x(i16 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 19 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 20 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 21 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 22 %group.size.x = load volatile i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 23 store i16 %group.size.x, i16 addrspace(1)* %out 24 ret void 25} 26 27; CHECK-LABEL: @load_group_size_x( 28; CHECK-NEXT: store i16 8, 29define amdgpu_kernel void @load_group_size_x(i16 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 30 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 31 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 32 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 33 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 34 store i16 %group.size.x, i16 addrspace(1)* %out 35 ret void 36} 37 38; CHECK-LABEL: @load_group_size_y( 39; CHECK-NEXT: store i16 16, 40define amdgpu_kernel void @load_group_size_y(i16 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 41 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 42 %gep.group.size.y = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 6 43 %gep.group.size.y.bc = bitcast i8 addrspace(4)* %gep.group.size.y to i16 addrspace(4)* 44 %group.size.y = load i16, i16 addrspace(4)* %gep.group.size.y.bc, align 4 45 store i16 %group.size.y, i16 addrspace(1)* %out 46 ret void 47} 48 49; CHECK-LABEL: @load_group_size_z( 50; CHECK-NEXT: store i16 2, 51define amdgpu_kernel void @load_group_size_z(i16 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 52 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 53 %gep.group.size.z = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 8 54 %gep.group.size.z.bc = bitcast i8 addrspace(4)* %gep.group.size.z to i16 addrspace(4)* 55 %group.size.z = load i16, i16 addrspace(4)* %gep.group.size.z.bc, align 4 56 store i16 %group.size.z, i16 addrspace(1)* %out 57 ret void 58} 59 60; Metadata uses i64 instead of i32 61; CHECK-LABEL: @load_group_size_x_reqd_work_group_size_i64( 62; CHECK-NEXT: store i16 8, 63define amdgpu_kernel void @load_group_size_x_reqd_work_group_size_i64(i16 addrspace(1)* %out) #0 !reqd_work_group_size !2 { 64 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 65 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 66 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 67 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 68 store i16 %group.size.x, i16 addrspace(1)* %out 69 ret void 70} 71 72; Metadata uses i16 instead of i32 73; CHECK-LABEL: @load_group_size_x_reqd_work_group_size_i16( 74; CHECK-NEXT: store i16 8, 75define amdgpu_kernel void @load_group_size_x_reqd_work_group_size_i16(i16 addrspace(1)* %out) #0 !reqd_work_group_size !3 { 76 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 77 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 78 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 79 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 80 store i16 %group.size.x, i16 addrspace(1)* %out 81 ret void 82} 83 84; CHECK-LABEL: @use_local_size_x_8_16_2( 85; CHECK-NEXT: store i64 8, 86define amdgpu_kernel void @use_local_size_x_8_16_2(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 87 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 88 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 89 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 90 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 91 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 92 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 93 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 94 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 95 %group.size.x.zext = zext i16 %group.size.x to i32 96 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 97 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 98 %cmp = icmp ult i32 %sub, %group.size.x.zext 99 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 100 %zext = zext i32 %select to i64 101 store i64 %zext, i64 addrspace(1)* %out 102 ret void 103} 104 105; CHECK-LABEL: @use_local_size_y_8_16_2( 106; CHECK-NEXT: store i64 16, 107define amdgpu_kernel void @use_local_size_y_8_16_2(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 108 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 109 %gep.group.size.y = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 6 110 %gep.group.size.y.bc = bitcast i8 addrspace(4)* %gep.group.size.y to i16 addrspace(4)* 111 %group.size.y = load i16, i16 addrspace(4)* %gep.group.size.y.bc, align 4 112 %gep.grid.size.y = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 16 113 %gep.grid.size.y.bc = bitcast i8 addrspace(4)* %gep.grid.size.y to i32 addrspace(4)* 114 %grid.size.y = load i32, i32 addrspace(4)* %gep.grid.size.y.bc, align 4 115 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.y() 116 %group.size.y.zext = zext i16 %group.size.y to i32 117 %group.id_x_group.size.y = mul i32 %group.id, %group.size.y.zext 118 %sub = sub i32 %grid.size.y, %group.id_x_group.size.y 119 %cmp = icmp ult i32 %sub, %group.size.y.zext 120 %select = select i1 %cmp, i32 %sub, i32 %group.size.y.zext 121 %zext = zext i32 %select to i64 122 store i64 %zext, i64 addrspace(1)* %out 123 ret void 124} 125 126; CHECK-LABEL: @use_local_size_z_8_16_2( 127; CHECK-NEXT: store i64 2, 128define amdgpu_kernel void @use_local_size_z_8_16_2(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 129 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 130 %gep.group.size.z = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 8 131 %gep.group.size.z.bc = bitcast i8 addrspace(4)* %gep.group.size.z to i16 addrspace(4)* 132 %group.size.z = load i16, i16 addrspace(4)* %gep.group.size.z.bc, align 4 133 %gep.grid.size.z = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 20 134 %gep.grid.size.z.bc = bitcast i8 addrspace(4)* %gep.grid.size.z to i32 addrspace(4)* 135 %grid.size.z = load i32, i32 addrspace(4)* %gep.grid.size.z.bc, align 4 136 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.z() 137 %group.size.z.zext = zext i16 %group.size.z to i32 138 %group.id_x_group.size.z = mul i32 %group.id, %group.size.z.zext 139 %sub = sub i32 %grid.size.z, %group.id_x_group.size.z 140 %cmp = icmp ult i32 %sub, %group.size.z.zext 141 %select = select i1 %cmp, i32 %sub, i32 %group.size.z.zext 142 %zext = zext i32 %select to i64 143 store i64 %zext, i64 addrspace(1)* %out 144 ret void 145} 146 147; Simplification on select is invalid, but we can still eliminate the 148; load of the group size. 149 150; CHECK-LABEL: @local_size_x_8_16_2_wrong_group_id( 151; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.y() 152; CHECK: %group.id_x_group.size.x.neg = mul i32 %group.id, -8 153define amdgpu_kernel void @local_size_x_8_16_2_wrong_group_id(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 154 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 155 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 156 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 157 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 158 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 159 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 160 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 161 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.y() 162 %group.size.x.zext = zext i16 %group.size.x to i32 163 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 164 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 165 %cmp = icmp ult i32 %sub, %group.size.x.zext 166 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 167 %zext = zext i32 %select to i64 168 store i64 %zext, i64 addrspace(1)* %out 169 ret void 170} 171 172; CHECK-LABEL: @local_size_x_8_16_2_wrong_grid_size( 173; CHECK: %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 174; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 175; CHECK: %group.id_x_group.size.x.neg = mul i32 %group.id, -8 176 define amdgpu_kernel void @local_size_x_8_16_2_wrong_grid_size(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 177 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 178 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 179 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 180 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 181 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 16 182 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 183 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 184 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 185 %group.size.x.zext = zext i16 %group.size.x to i32 186 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 187 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 188 %cmp = icmp ult i32 %sub, %group.size.x.zext 189 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 190 %zext = zext i32 %select to i64 191 store i64 %zext, i64 addrspace(1)* %out 192 ret void 193} 194 195; CHECK-LABEL: @local_size_x_8_16_2_wrong_cmp_type( 196; CHECK: %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 197; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 198; CHECK: %group.id_x_group.size.x.neg = mul i32 %group.id, -8 199; CHECK: %sub = add i32 %group.id_x_group.size.x.neg, %grid.size.x 200; CHECK: %cmp = icmp slt i32 %sub, 8 201; CHECK: %select = select i1 %cmp, i32 %sub, i32 8 202define amdgpu_kernel void @local_size_x_8_16_2_wrong_cmp_type(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 203 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 204 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 205 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 206 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 207 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 208 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 209 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 210 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 211 %group.size.x.zext = zext i16 %group.size.x to i32 212 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 213 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 214 %cmp = icmp slt i32 %sub, %group.size.x.zext 215 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 216 %zext = zext i32 %select to i64 217 store i64 %zext, i64 addrspace(1)* %out 218 ret void 219} 220 221; CHECK-LABEL: @local_size_x_8_16_2_wrong_select( 222; CHECK: %group.id_x_group.size.x.neg = mul i32 %group.id, -8 223; CHECK: %sub = add i32 %group.id_x_group.size.x.neg, %grid.size.x 224; CHECK: %1 = icmp ugt i32 %sub, 8 225; CHECK: %select = select i1 %1, i32 %sub, i32 8 226; CHECK: %zext = zext i32 %select to i64 227define amdgpu_kernel void @local_size_x_8_16_2_wrong_select(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 228 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 229 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 230 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 231 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 232 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 233 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 234 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 235 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 236 %group.size.x.zext = zext i16 %group.size.x to i32 237 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 238 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 239 %cmp = icmp ult i32 %sub, %group.size.x.zext 240 %select = select i1 %cmp, i32 %group.size.x.zext, i32 %sub 241 %zext = zext i32 %select to i64 242 store i64 %zext, i64 addrspace(1)* %out 243 ret void 244} 245 246; CHECK-LABEL: @use_local_size_x_8_16_2_wrong_grid_load_size( 247; CHECK: %grid.size.x = load i16, i16 addrspace(4)* %gep.grid.size.x.bc, align 4 248; CHECK: %grid.size.x.zext = zext i16 %grid.size.x to i32 249; CHECK: %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 250; CHECK: %group.id_x_group.size.x.neg = mul i32 %group.id, -8 251; CHECK: %sub = add i32 %group.id_x_group.size.x.neg, %grid.size.x.zext 252define amdgpu_kernel void @use_local_size_x_8_16_2_wrong_grid_load_size(i64 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 253 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 254 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 255 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 256 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 257 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 258 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i16 addrspace(4)* 259 %grid.size.x = load i16, i16 addrspace(4)* %gep.grid.size.x.bc, align 4 260 %grid.size.x.zext = zext i16 %grid.size.x to i32 261 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 262 %group.size.x.zext = zext i16 %group.size.x to i32 263 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 264 %sub = sub i32 %grid.size.x.zext, %group.id_x_group.size.x 265 %cmp = icmp ult i32 %sub, %group.size.x.zext 266 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 267 %zext = zext i32 %select to i64 268 store i64 %zext, i64 addrspace(1)* %out 269 ret void 270} 271 272; CHECK-LABEL: @func_group_size_x( 273; CHECK-NEXT: ret i32 8 274define i32 @func_group_size_x(i16 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 275 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 276 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 277 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 278 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 279 %zext = zext i16 %group.size.x to i32 280 ret i32 %zext 281} 282 283; CHECK-LABEL: @__ockl_get_local_size_reqd_size( 284; CHECK: %group.size = phi i32 [ 2, %bb17 ], [ 16, %bb9 ], [ 8, %bb1 ], [ 1, %bb ] 285define i64 @__ockl_get_local_size_reqd_size(i32 %arg) #1 !reqd_work_group_size !0 { 286bb: 287 %tmp = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #2 288 switch i32 %arg, label %bb25 [ 289 i32 0, label %bb1 290 i32 1, label %bb9 291 i32 2, label %bb17 292 ] 293 294bb1: ; preds = %bb 295 %tmp2 = tail call i32 @llvm.amdgcn.workgroup.id.x() 296 %tmp3 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 12 297 %tmp4 = bitcast i8 addrspace(4)* %tmp3 to i32 addrspace(4)* 298 %tmp5 = load i32, i32 addrspace(4)* %tmp4, align 4 299 %tmp6 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 4 300 %tmp7 = bitcast i8 addrspace(4)* %tmp6 to i16 addrspace(4)* 301 %tmp8 = load i16, i16 addrspace(4)* %tmp7, align 4 302 br label %bb25 303 304bb9: ; preds = %bb 305 %tmp10 = tail call i32 @llvm.amdgcn.workgroup.id.y() 306 %tmp11 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 16 307 %tmp12 = bitcast i8 addrspace(4)* %tmp11 to i32 addrspace(4)* 308 %tmp13 = load i32, i32 addrspace(4)* %tmp12, align 8 309 %tmp14 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 6 310 %tmp15 = bitcast i8 addrspace(4)* %tmp14 to i16 addrspace(4)* 311 %tmp16 = load i16, i16 addrspace(4)* %tmp15, align 2 312 br label %bb25 313 314bb17: ; preds = %bb 315 %tmp18 = tail call i32 @llvm.amdgcn.workgroup.id.z() 316 %tmp19 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 20 317 %tmp20 = bitcast i8 addrspace(4)* %tmp19 to i32 addrspace(4)* 318 %tmp21 = load i32, i32 addrspace(4)* %tmp20, align 4 319 %tmp22 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 8 320 %tmp23 = bitcast i8 addrspace(4)* %tmp22 to i16 addrspace(4)* 321 %tmp24 = load i16, i16 addrspace(4)* %tmp23, align 8 322 br label %bb25 323 324bb25: ; preds = %bb17, %bb9, %bb1, %bb 325 %tmp26 = phi i32 [ %tmp21, %bb17 ], [ %tmp13, %bb9 ], [ %tmp5, %bb1 ], [ 0, %bb ] 326 %group.size = phi i16 [ %tmp24, %bb17 ], [ %tmp16, %bb9 ], [ %tmp8, %bb1 ], [ 1, %bb ] 327 %tmp28 = phi i32 [ %tmp18, %bb17 ], [ %tmp10, %bb9 ], [ %tmp2, %bb1 ], [ 0, %bb ] 328 %tmp29 = zext i16 %group.size to i32 329 %tmp30 = mul i32 %tmp28, %tmp29 330 %tmp31 = sub i32 %tmp26, %tmp30 331 %tmp32 = icmp ult i32 %tmp31, %tmp29 332 %tmp33 = select i1 %tmp32, i32 %tmp31, i32 %tmp29 333 %tmp34 = zext i32 %tmp33 to i64 334 ret i64 %tmp34 335} 336 337; CHECK-LABEL: @all_local_size( 338; CHECK-NEXT: store volatile i64 8, i64 addrspace(1)* %out, align 4 339; CHECK-NEXT: store volatile i64 16, i64 addrspace(1)* %out, align 4 340; CHECK-NEXT: store volatile i64 2, i64 addrspace(1)* %out, align 4 341define amdgpu_kernel void @all_local_size(i64 addrspace(1)* nocapture readnone %out) #0 !reqd_work_group_size !0 { 342 %tmp.i = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 343 %tmp2.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #0 344 %tmp3.i = getelementptr inbounds i8, i8 addrspace(4)* %tmp.i, i64 12 345 %tmp4.i = bitcast i8 addrspace(4)* %tmp3.i to i32 addrspace(4)* 346 %tmp5.i = load i32, i32 addrspace(4)* %tmp4.i, align 4 347 %tmp6.i = getelementptr inbounds i8, i8 addrspace(4)* %tmp.i, i64 4 348 %tmp7.i = bitcast i8 addrspace(4)* %tmp6.i to i16 addrspace(4)* 349 %tmp8.i = load i16, i16 addrspace(4)* %tmp7.i, align 4 350 %tmp29.i = zext i16 %tmp8.i to i32 351 %tmp30.i = mul i32 %tmp2.i, %tmp29.i 352 %tmp31.i = sub i32 %tmp5.i, %tmp30.i 353 %tmp32.i = icmp ult i32 %tmp31.i, %tmp29.i 354 %tmp33.i = select i1 %tmp32.i, i32 %tmp31.i, i32 %tmp29.i 355 %tmp34.i = zext i32 %tmp33.i to i64 356 %tmp10.i = tail call i32 @llvm.amdgcn.workgroup.id.y() #0 357 %tmp11.i = getelementptr inbounds i8, i8 addrspace(4)* %tmp.i, i64 16 358 %tmp12.i = bitcast i8 addrspace(4)* %tmp11.i to i32 addrspace(4)* 359 %tmp13.i = load i32, i32 addrspace(4)* %tmp12.i, align 8 360 %tmp14.i = getelementptr inbounds i8, i8 addrspace(4)* %tmp.i, i64 6 361 %tmp15.i = bitcast i8 addrspace(4)* %tmp14.i to i16 addrspace(4)* 362 %tmp16.i = load i16, i16 addrspace(4)* %tmp15.i, align 2 363 %tmp29.i9 = zext i16 %tmp16.i to i32 364 %tmp30.i10 = mul i32 %tmp10.i, %tmp29.i9 365 %tmp31.i11 = sub i32 %tmp13.i, %tmp30.i10 366 %tmp32.i12 = icmp ult i32 %tmp31.i11, %tmp29.i9 367 %tmp33.i13 = select i1 %tmp32.i12, i32 %tmp31.i11, i32 %tmp29.i9 368 %tmp34.i14 = zext i32 %tmp33.i13 to i64 369 %tmp18.i = tail call i32 @llvm.amdgcn.workgroup.id.z() #0 370 %tmp19.i = getelementptr inbounds i8, i8 addrspace(4)* %tmp.i, i64 20 371 %tmp20.i = bitcast i8 addrspace(4)* %tmp19.i to i32 addrspace(4)* 372 %tmp21.i = load i32, i32 addrspace(4)* %tmp20.i, align 4 373 %tmp22.i = getelementptr inbounds i8, i8 addrspace(4)* %tmp.i, i64 8 374 %tmp23.i = bitcast i8 addrspace(4)* %tmp22.i to i16 addrspace(4)* 375 %tmp24.i = load i16, i16 addrspace(4)* %tmp23.i, align 8 376 %tmp29.i2 = zext i16 %tmp24.i to i32 377 %tmp30.i3 = mul i32 %tmp18.i, %tmp29.i2 378 %tmp31.i4 = sub i32 %tmp21.i, %tmp30.i3 379 %tmp32.i5 = icmp ult i32 %tmp31.i4, %tmp29.i2 380 %tmp33.i6 = select i1 %tmp32.i5, i32 %tmp31.i4, i32 %tmp29.i2 381 %tmp34.i7 = zext i32 %tmp33.i6 to i64 382 store volatile i64 %tmp34.i, i64 addrspace(1)* %out, align 4 383 store volatile i64 %tmp34.i14, i64 addrspace(1)* %out, align 4 384 store volatile i64 %tmp34.i7, i64 addrspace(1)* %out, align 4 385 ret void 386} 387 388; TODO: Should be able to handle this, but not much reason to. 389; CHECK-LABEL: @partial_load_group_size_x( 390; CHECK-NEXT: %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 391; CHECK-NEXT: %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 392; CHECK-NEXT: %group.size.x.lo = load i8, i8 addrspace(4)* %gep.group.size.x, align 4 393; CHECK-NEXT: store i8 %group.size.x.lo, i8 addrspace(1)* %out, align 1 394define amdgpu_kernel void @partial_load_group_size_x(i8 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 395 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 396 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 397 %group.size.x.lo = load i8, i8 addrspace(4)* %gep.group.size.x, align 1 398 store i8 %group.size.x.lo, i8 addrspace(1)* %out 399 ret void 400} 401 402; CHECK-LABEL: @partial_load_group_size_x_explicit_callsite_align( 403; CHECK-NEXT: %dispatch.ptr = tail call align 2 i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 404; CHECK-NEXT: %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 405; CHECK-NEXT: %group.size.x.lo = load i8, i8 addrspace(4)* %gep.group.size.x, align 2 406; CHECK-NEXT: store i8 %group.size.x.lo, i8 addrspace(1)* %out, align 1 407define amdgpu_kernel void @partial_load_group_size_x_explicit_callsite_align(i8 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 408 %dispatch.ptr = tail call align 2 i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 409 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 410 %group.size.x.lo = load i8, i8 addrspace(4)* %gep.group.size.x, align 1 411 store i8 %group.size.x.lo, i8 addrspace(1)* %out 412 ret void 413} 414 415; TODO: Should be able to handle this 416; CHECK-LABEL: @load_group_size_xy_i32( 417; CHECK: %group.size.xy = load i32, 418; CHECK: store i32 %group.size.xy 419define amdgpu_kernel void @load_group_size_xy_i32(i32 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 420 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 421 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 422 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i32 addrspace(4)* 423 %group.size.xy = load i32, i32 addrspace(4)* %gep.group.size.x.bc, align 4 424 store i32 %group.size.xy, i32 addrspace(1)* %out 425 ret void 426} 427 428; CHECK-LABEL: @load_group_size_x_y_multiple_dispatch_ptr( 429; CHECK-NEXT: store volatile i16 8, i16 addrspace(1)* %out, align 2 430; CHECK-NEXT: store volatile i16 16, i16 addrspace(1)* %out, align 2 431define amdgpu_kernel void @load_group_size_x_y_multiple_dispatch_ptr(i16 addrspace(1)* %out) #0 !reqd_work_group_size !0 { 432 %dispatch.ptr0 = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 433 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr0, i64 4 434 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 435 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 436 store volatile i16 %group.size.x, i16 addrspace(1)* %out 437 438 %dispatch.ptr1 = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 439 %gep.group.size.y = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr1, i64 6 440 %gep.group.size.y.bc = bitcast i8 addrspace(4)* %gep.group.size.y to i16 addrspace(4)* 441 %group.size.y = load i16, i16 addrspace(4)* %gep.group.size.y.bc, align 4 442 store volatile i16 %group.size.y, i16 addrspace(1)* %out 443 444 ret void 445} 446 447; CHECK-LABEL: @use_local_size_x_uniform_work_group_size( 448; CHECK-NEXT: %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 449; CHECK-NEXT: %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 450; CHECK-NEXT: %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 451; CHECK-NEXT: %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 452; CHECK-NEXT: %zext = zext i16 %group.size.x to i64 453; CHECK-NEXT: store i64 %zext, i64 addrspace(1)* %out, align 4 454define amdgpu_kernel void @use_local_size_x_uniform_work_group_size(i64 addrspace(1)* %out) #2 { 455 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 456 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 457 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 458 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 459 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 460 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 461 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 462 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 463 %group.size.x.zext = zext i16 %group.size.x to i32 464 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 465 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 466 %cmp = icmp ult i32 %sub, %group.size.x.zext 467 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 468 %zext = zext i32 %select to i64 469 store i64 %zext, i64 addrspace(1)* %out 470 ret void 471} 472 473; CHECK-LABEL: @use_local_size_x_uniform_work_group_size_false( 474; CHECK: icmp ult 475; CHECK: select 476define amdgpu_kernel void @use_local_size_x_uniform_work_group_size_false(i64 addrspace(1)* %out) #3 { 477 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 478 %gep.group.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 4 479 %gep.group.size.x.bc = bitcast i8 addrspace(4)* %gep.group.size.x to i16 addrspace(4)* 480 %group.size.x = load i16, i16 addrspace(4)* %gep.group.size.x.bc, align 4 481 %gep.grid.size.x = getelementptr inbounds i8, i8 addrspace(4)* %dispatch.ptr, i64 12 482 %gep.grid.size.x.bc = bitcast i8 addrspace(4)* %gep.grid.size.x to i32 addrspace(4)* 483 %grid.size.x = load i32, i32 addrspace(4)* %gep.grid.size.x.bc, align 4 484 %group.id = tail call i32 @llvm.amdgcn.workgroup.id.x() 485 %group.size.x.zext = zext i16 %group.size.x to i32 486 %group.id_x_group.size.x = mul i32 %group.id, %group.size.x.zext 487 %sub = sub i32 %grid.size.x, %group.id_x_group.size.x 488 %cmp = icmp ult i32 %sub, %group.size.x.zext 489 %select = select i1 %cmp, i32 %sub, i32 %group.size.x.zext 490 %zext = zext i32 %select to i64 491 store i64 %zext, i64 addrspace(1)* %out 492 ret void 493} 494 495; CHECK-LABEL: @no_use_dispatch_ptr( 496; CHECK-NEXT: ret void 497define amdgpu_kernel void @no_use_dispatch_ptr() { 498 %dispatch.ptr = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 499 ret void 500} 501 502declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #1 503declare i32 @llvm.amdgcn.workgroup.id.x() #1 504declare i32 @llvm.amdgcn.workgroup.id.y() #1 505declare i32 @llvm.amdgcn.workgroup.id.z() #1 506 507attributes #0 = { nounwind "uniform-work-group-size"="true" } 508attributes #1 = { nounwind readnone speculatable } 509attributes #2 = { nounwind "uniform-work-group-size"="true" } 510attributes #3 = { nounwind "uniform-work-group-size"="false" } 511 512!0 = !{i32 8, i32 16, i32 2} 513!1 = !{i32 8, i32 16} 514!2 = !{i64 8, i64 16, i64 2} 515!3 = !{i16 8, i16 16, i16 2} 516