1; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck -check-prefixes=SI,GCN %s
2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=VI,GCN %s
3
4; GCN-LABEL: {{^}}select0:
5; i64 select should be split into two i32 selects, and we shouldn't need
6; to use a shfit to extract the hi dword of the input.
7; GCN-NOT: s_lshr_b64
8; GCN: v_cndmask
9; GCN: v_cndmask
10define amdgpu_kernel void @select0(i64 addrspace(1)* %out, i32 %cond, i64 %in) {
11entry:
12  %0 = icmp ugt i32 %cond, 5
13  %1 = select i1 %0, i64 0, i64 %in
14  store i64 %1, i64 addrspace(1)* %out
15  ret void
16}
17
18; GCN-LABEL: {{^}}select_trunc_i64:
19; VI: s_cselect_b32
20; VI-NOT: s_cselect_b32
21; SI: v_cndmask_b32
22; SI-NOT: v_cndmask_b32
23define amdgpu_kernel void @select_trunc_i64(i32 addrspace(1)* %out, i32 %cond, i64 %in) nounwind {
24  %cmp = icmp ugt i32 %cond, 5
25  %sel = select i1 %cmp, i64 0, i64 %in
26  %trunc = trunc i64 %sel to i32
27  store i32 %trunc, i32 addrspace(1)* %out, align 4
28  ret void
29}
30
31; GCN-LABEL: {{^}}select_trunc_i64_2:
32; VI: s_cselect_b32
33; VI-NOT: s_cselect_b32
34; SI: v_cndmask_b32
35; SI-NOT: v_cndmask_b32
36define amdgpu_kernel void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 %b) nounwind {
37  %cmp = icmp ugt i32 %cond, 5
38  %sel = select i1 %cmp, i64 %a, i64 %b
39  %trunc = trunc i64 %sel to i32
40  store i32 %trunc, i32 addrspace(1)* %out, align 4
41  ret void
42}
43
44; GCN-LABEL: {{^}}v_select_trunc_i64_2:
45; VI: s_cselect_b32
46; VI-NOT: s_cselect_b32
47; SI: v_cndmask_b32
48; SI-NOT: v_cndmask_b32
49define amdgpu_kernel void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
50  %cmp = icmp ugt i32 %cond, 5
51  %a = load i64, i64 addrspace(1)* %aptr, align 8
52  %b = load i64, i64 addrspace(1)* %bptr, align 8
53  %sel = select i1 %cmp, i64 %a, i64 %b
54  %trunc = trunc i64 %sel to i32
55  store i32 %trunc, i32 addrspace(1)* %out, align 4
56  ret void
57}
58
59; GCN-LABEL: {{^}}v_select_i64_split_imm:
60; GCN-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
61; GCN-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}}
62; GCN: s_endpgm
63define amdgpu_kernel void @v_select_i64_split_imm(i64 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
64  %cmp = icmp ugt i32 %cond, 5
65  %a = load i64, i64 addrspace(1)* %aptr, align 8
66  %b = load i64, i64 addrspace(1)* %bptr, align 8
67  %sel = select i1 %cmp, i64 %a, i64 270582939648 ; 63 << 32
68  store i64 %sel, i64 addrspace(1)* %out, align 8
69  ret void
70}
71