1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s 2define void @test() #1 { 3 ; Clean up the unreachable blocks introduced with LowerSwitch pass. 4 ; This test ensures that, in the pass flow, UnreachableBlockElim pass 5 ; follows the LowerSwitch. Otherwise, this testcase will crash 6 ; immediately after the instruction selection due to the incomplete 7 ; PHI node in an MBB whose incoming values were never codegenerated. 8 ; 9 ; GCN-LABEL: name: test 10 ; GCN: bb.{{[0-9]+}}.entry: 11 ; GCN: bb.{{[0-9]+}}.entry.true.blk: 12 ; GCN: bb.{{[0-9]+}}.entry.false.blk: 13 ; GCN: bb.{{[0-9]+}}.switch.blk: 14 15 ; GCN-NOT: bb.{{[0-9]+}}.preheader.blk 16 ; GCN-NOT: bb.{{[0-9]+}}.pre.false.blk: 17 ; GCN-NOT: bb.{{[0-9]+}}.unreach.blk: 18 ; GCN-NOT: PHI 19 20 ; GCN: bb.{{[0-9]+}}.exit: 21 entry: 22 %idx = tail call i32 @llvm.amdgcn.workitem.id.x() #0 23 br i1 undef, label %entry.true.blk, label %entry.false.blk 24 25 entry.true.blk: ; preds = %entry 26 %exit.cmp = icmp ult i32 %idx, 3 27 br i1 %exit.cmp, label %switch.blk, label %exit 28 29 entry.false.blk: ; preds = %entry 30 unreachable 31 32 switch.blk: ; preds = %entry.true.blk 33 switch i32 %idx, label %preheader.blk [ 34 i32 0, label %exit 35 i32 1, label %exit 36 i32 2, label %exit 37 ] 38 39 preheader.blk: ; preds = %switch.blk 40 %pre.exit = icmp ult i32 %idx, 5 41 br i1 %pre.exit, label %unreach.blk, label %pre.false.blk 42 43 pre.false.blk: ; preds = %preheader.blk 44 %call.pre.false = tail call i32 @func(i32 %idx) #0 45 br label %unreach.blk 46 47 unreach.blk: ; preds = %preheader.blk, %pre.false.blk 48 %phi.val = phi i32 [ %call.pre.false, %pre.false.blk ], [ undef, %preheader.blk ] 49 store i32 %phi.val, i32* undef 50 unreachable 51 52 exit: ; preds = %switch.blk 53 ret void 54} 55 56declare i32 @llvm.amdgcn.workitem.id.x() #0 57declare i32 @func(i32)#0 58 59attributes #0 = { nounwind readnone } 60attributes #1 = { nounwind } 61