1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
3
4
5; GCN-LABEL: {{^}}global_truncstore_i32_to_i1:
6; GCN: s_load_dword [[LOAD:s[0-9]+]],
7; GCN: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
8; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9; GCN: buffer_store_byte [[VREG]],
10define amdgpu_kernel void @global_truncstore_i32_to_i1(i1 addrspace(1)* %out, i32 %val) nounwind {
11  %trunc = trunc i32 %val to i1
12  store i1 %trunc, i1 addrspace(1)* %out, align 1
13  ret void
14}
15
16; GCN-LABEL: {{^}}global_truncstore_i64_to_i1:
17; GCN: buffer_store_byte
18define amdgpu_kernel void @global_truncstore_i64_to_i1(i1 addrspace(1)* %out, i64 %val) nounwind {
19  %trunc = trunc i64 %val to i1
20  store i1 %trunc, i1 addrspace(1)* %out, align 1
21  ret void
22}
23
24; FIXME: VGPR on VI
25; GCN-LABEL: {{^}}s_arg_global_truncstore_i16_to_i1:
26; GCN: s_load_dword [[LOAD:s[0-9]+]],
27; GCN: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
28; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
29; GCN: buffer_store_byte [[VREG]],
30define amdgpu_kernel void @s_arg_global_truncstore_i16_to_i1(i1 addrspace(1)* %out, i16 %val) nounwind {
31  %trunc = trunc i16 %val to i1
32  store i1 %trunc, i1 addrspace(1)* %out, align 1
33  ret void
34}
35; GCN-LABEL: {{^}}global_truncstore_i16_to_i1:
36define amdgpu_kernel void @global_truncstore_i16_to_i1(i1 addrspace(1)* %out, i16 %val0, i16 %val1) nounwind {
37  %add = add i16 %val0, %val1
38  %trunc = trunc i16 %add to i1
39  store i1 %trunc, i1 addrspace(1)* %out, align 1
40  ret void
41}
42