1; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
3
4; GCN-LABEL: {{^}}icmp_2_users:
5; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1
6; GCN: s_cbranch_scc1 [[LABEL:BB[0-9_A-Z]+]]
7; GCN: [[LABEL]]:
8; GCN-NEXT: s_endpgm
9define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) {
10main_body:
11  %0 = icmp sgt i32 %cond, 0
12  %1 = sext i1 %0 to i32
13  br i1 %0, label %IF, label %ENDIF
14
15IF:
16  store i32 %1, i32 addrspace(1)* %out
17  br label %ENDIF
18
19ENDIF:                                            ; preds = %IF, %main_body
20  ret void
21}
22
23; GCN-LABEL: {{^}}fix_sgpr_live_ranges_crash:
24; GCN: s_cbranch_scc1 [[BB0:[A-Z0-9_]+]]
25; GCN: {{^}}[[LOOP:[A-Z0-9_]+]]:
26; GCN: s_cbranch_scc1 [[LOOP]]
27; GCN: {{^}}[[BB0]]:
28define amdgpu_kernel void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1)  {
29bb:
30  %cnd = trunc i32 %arg to i1
31  br i1 %cnd, label %bb2, label %bb5
32
33bb2:                                              ; preds = %bb
34  %tmp = mul i32 10, %arg1
35  br label %bb3
36
37bb3:                                              ; preds = %bb3, %bb2
38  %val = load volatile i32, i32 addrspace(4)* undef
39  %tmp4 = icmp eq i32 %val, %arg1
40  br i1 %tmp4, label %bb5, label %bb3
41
42bb5:                                              ; preds = %bb3, %bb
43  %tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #1
44  %tmp10 = icmp ult i32 %tmp6, %arg
45  br i1 %tmp10, label %bb11, label %bb12
46
47bb11:                                             ; preds = %bb11, %bb5
48  br i1 undef, label %bb11, label %bb12
49
50bb12:                                             ; preds = %bb11, %bb5
51  ret void
52}
53
54; Function Attrs: nounwind readnone
55declare i32 @llvm.amdgcn.workitem.id.y() #1
56
57attributes #1 = { nounwind readnone }
58