1; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
4
5; This compute shader has input args that claim that it has 17 sgprs and 5 vgprs
6; in wave dispatch. Ensure that the sgpr and vgpr counts in COMPUTE_PGM_RSRC1
7; are set to reflect that, even though the registers are not used in the shader.
8
9; GCN-LABEL: {{^}}_amdgpu_cs_main:
10; GCN:         .amdgpu_pal_metadata
11; GCN-NEXT: ---
12; GCN-NEXT: amdpal.pipelines:
13; GCN-NEXT:   - .hardware_stages:
14; GCN-NEXT:       .cs:
15; GCN-NEXT:         .entry_point:    _amdgpu_cs_main
16; GCN-NEXT:         .scratch_memory_size: 0
17; SI-NEXT:          .sgpr_count:     0x11
18; VI-NEXT:          .sgpr_count:     0x60
19; GFX9-NEXT:        .sgpr_count:     0x11
20; SI-NEXT:          .vgpr_count:     0x5
21; VI-NEXT:          .vgpr_count:     0x5
22; GFX9-NEXT:        .vgpr_count:     0x5
23; GCN-NEXT:     .registers:
24; SI-NEXT:        0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81
25; VI-NEXT:        0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}c1
26; GFX9-NEXT:      0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81
27; GCN-NEXT:       0x2e13 (COMPUTE_PGM_RSRC2): 0
28; GCN-NEXT: ...
29; GCN-NEXT:         .end_amdgpu_pal_metadata
30
31define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, <2 x i32> inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <5 x i32>) {
32.entry:
33  ret void
34}
35