1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2
3; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to
4; create vselects with i64 condition masks.
5
6; FIXME: Should be able to avoid intermediate vselect
7; GCN-LABEL: {{^}}widen_vselect_and_mask_v4f64:
8; GCN: v_cmp_u_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]],
9; GCN: v_cndmask_b32_e64 v[[VSEL:[0-9]+]], 0, -1, [[CMP]]
10; GCN: v_mov_b32_e32 v[[VSEL_EXT:[0-9]+]], v[[VSEL]]
11; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[VSEL]]:[[VSEL_EXT]]{{\]}}
12define amdgpu_kernel void @widen_vselect_and_mask_v4f64(<4 x double> %arg) #0 {
13bb:
14  %tmp = extractelement <4 x double> %arg, i64 0
15  %tmp1 = fcmp uno double %tmp, 0.000000e+00
16  %tmp2 = sext i1 %tmp1 to i64
17  %tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0
18  %tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1
19  %tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2
20  %tmp6 = insertelement <4 x i64> %tmp5, i64 undef, i32 3
21  %tmp7 = fcmp une <4 x double> %arg, zeroinitializer
22  %tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
23  %tmp9 = and <4 x i1> %tmp8, %tmp7
24  %tmp10 = select <4 x i1> %tmp9, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, <4 x double> zeroinitializer
25  store <4 x double> %tmp10, <4 x double> addrspace(1)* null, align 32
26  ret void
27}
28
29; GCN-LABEL: {{^}}widen_vselect_and_mask_v4i64:
30; GCN: v_cmp_eq_u64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]],
31; GCN: v_cndmask_b32_e64 v[[VSEL:[0-9]+]], 0, -1, [[CMP]]
32; GCN: v_mov_b32_e32 v[[VSEL_EXT:[0-9]+]], v[[VSEL]]
33; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[}}[[VSEL]]:[[VSEL_EXT]]{{\]}}
34define amdgpu_kernel void @widen_vselect_and_mask_v4i64(<4 x i64> %arg) #0 {
35bb:
36  %tmp = extractelement <4 x i64> %arg, i64 0
37  %tmp1 = icmp eq i64 %tmp, 0
38  %tmp2 = sext i1 %tmp1 to i64
39  %tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0
40  %tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1
41  %tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2
42  %tmp6 = insertelement <4 x i64> %tmp5, i64 undef, i32 3
43  %tmp7 = icmp ne <4 x i64> %arg, zeroinitializer
44  %tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
45  %tmp9 = and <4 x i1> %tmp8, %tmp7
46  %tmp10 = select <4 x i1> %tmp9, <4 x i64> <i64 1, i64 1, i64 1, i64 1>, <4 x i64> zeroinitializer
47  store <4 x i64> %tmp10, <4 x i64> addrspace(1)* null, align 32
48  ret void
49}
50
51attributes #0 = { nounwind }
52attributes #1 = { nounwind readnone speculatable }
53