1; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s
2
3declare void @llvm.write_register.i32(metadata, i32) #0
4declare void @llvm.write_register.i64(metadata, i64) #0
5
6; CHECK-LABEL: {{^}}test_write_m0:
7define amdgpu_kernel void @test_write_m0(i32 %val) #0 {
8  call void @llvm.write_register.i32(metadata !0, i32 0)
9  call void @llvm.write_register.i32(metadata !0, i32 -1)
10  call void @llvm.write_register.i32(metadata !0, i32 %val)
11  call void @llvm.amdgcn.wave.barrier() #1
12  ret void
13}
14
15; CHECK-LABEL: {{^}}test_write_exec:
16; CHECK: s_mov_b64 exec, 0
17; CHECK: s_mov_b64 exec, -1
18; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}}
19define amdgpu_kernel void @test_write_exec(i64 %val) #0 {
20  call void @llvm.write_register.i64(metadata !1, i64 0)
21  call void @llvm.write_register.i64(metadata !1, i64 -1)
22  call void @llvm.write_register.i64(metadata !1, i64 %val)
23  call void @llvm.amdgcn.wave.barrier() #1
24  ret void
25}
26
27; CHECK-LABEL: {{^}}test_write_flat_scratch_0:
28; CHECK: s_mov_b64 flat_scratch, 0
29define amdgpu_kernel void @test_write_flat_scratch_0(i64 %val) #0 {
30  call void @llvm.write_register.i64(metadata !2, i64 0)
31  call void @llvm.amdgcn.wave.barrier() #1
32  ret void
33}
34
35; CHECK-LABEL: {{^}}test_write_flat_scratch_neg1:
36; CHECK: s_mov_b64 flat_scratch, -1
37define amdgpu_kernel void @test_write_flat_scratch_neg1(i64 %val) #0 {
38  call void @llvm.write_register.i64(metadata !2, i64 -1)
39  call void @llvm.amdgcn.wave.barrier() #1
40  ret void
41}
42
43; CHECK-LABEL: {{^}}test_write_flat_scratch_val:
44; CHECK: s_load_dwordx2 flat_scratch, s{{\[[0-9]+:[0-9]+\]}}
45define amdgpu_kernel void @test_write_flat_scratch_val(i64 %val) #0 {
46  call void @llvm.write_register.i64(metadata !2, i64 %val)
47  call void @llvm.amdgcn.wave.barrier() #1
48  ret void
49}
50
51; CHECK-LABEL: {{^}}test_write_flat_scratch_lo:
52; CHECK: s_mov_b32 flat_scratch_lo, 0
53; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
54define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 {
55  call void @llvm.write_register.i32(metadata !3, i32 0)
56  call void @llvm.write_register.i32(metadata !3, i32 %val)
57  call void @llvm.amdgcn.wave.barrier() #1
58  ret void
59}
60
61; CHECK-LABEL: {{^}}test_write_flat_scratch_hi:
62; CHECK: s_mov_b32 flat_scratch_hi, 0
63; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
64define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 {
65  call void @llvm.write_register.i32(metadata !4, i32 0)
66  call void @llvm.write_register.i32(metadata !4, i32 %val)
67  call void @llvm.amdgcn.wave.barrier() #1
68  ret void
69}
70
71; CHECK-LABEL: {{^}}test_write_exec_lo:
72; CHECK: s_mov_b32 exec_lo, 0
73; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
74define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 {
75  call void @llvm.write_register.i32(metadata !5, i32 0)
76  call void @llvm.write_register.i32(metadata !5, i32 %val)
77  call void @llvm.amdgcn.wave.barrier() #1
78  ret void
79}
80
81; CHECK-LABEL: {{^}}test_write_exec_hi:
82; CHECK: s_mov_b32 exec_hi, 0
83; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
84define amdgpu_kernel void @test_write_exec_hi(i32 %val) #0 {
85  call void @llvm.write_register.i32(metadata !6, i32 0)
86  call void @llvm.write_register.i32(metadata !6, i32 %val)
87  call void @llvm.amdgcn.wave.barrier() #1
88  ret void
89}
90
91declare void @llvm.amdgcn.wave.barrier() #1
92
93attributes #0 = { nounwind }
94attributes #1 = { convergent nounwind }
95
96!0 = !{!"m0"}
97!1 = !{!"exec"}
98!2 = !{!"flat_scratch"}
99!3 = !{!"flat_scratch_lo"}
100!4 = !{!"flat_scratch_hi"}
101!5 = !{!"exec_lo"}
102!6 = !{!"exec_hi"}
103