1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}zext_or_operand_i64:
4; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
5; GCN: buffer_load_dword v[[LD32:[0-9]+]]
6; GCN-NOT: _or_
7; GCN-NOT: v[[HI]]
8; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
9; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]]
10; GCN-NOT: _or_
11; GCN-NOT: v[[HI]]
12; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
13; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
14define amdgpu_kernel void @zext_or_operand_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
15  %ld.64 = load volatile i64, i64 addrspace(1)* %in0
16  %ld.32 = load volatile i32, i32 addrspace(1)* %in1
17  %ext = zext i32 %ld.32 to i64
18  %or = or i64 %ld.64, %ext
19  store i64 %or, i64 addrspace(1)* %out
20  ret void
21}
22
23; GCN-LABEL: {{^}}zext_or_operand_commute_i64:
24; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
25; GCN: buffer_load_dword v[[LD32:[0-9]+]]
26; GCN-NOT: _or_
27; GCN-NOT: v[[HI]]
28; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
29; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]]
30; GCN-NOT: v[[HI]]
31; GCN-NOT: _or_
32; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
33; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
34define amdgpu_kernel void @zext_or_operand_commute_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
35  %ld.64 = load volatile i64, i64 addrspace(1)* %in0
36  %ld.32 = load volatile i32, i32 addrspace(1)* %in1
37  %ext = zext i32 %ld.32 to i64
38  %or = or i64 %ext, %ld.64
39  store i64 %or, i64 addrspace(1)* %out
40  ret void
41}
42