1# RUN: llc -O0 -mtriple arm-- -mattr=+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP3
3# RUN: llc -O0 -mtriple arm-- -mattr=+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
4# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP2
5--- |
6  define void @test_fpconst_zero_s32() { ret void }
7  define void @test_fpconst_zero_s64() { ret void }
8
9  define void @test_fpconst_8bit_s32() { ret void }
10  define void @test_fpconst_8bit_s64() { ret void }
11...
12---
13name:            test_fpconst_zero_s32
14# CHECK-LABEL: name: test_fpconst_zero_s32
15legalized:       true
16regBankSelected: true
17selected:        false
18# CHECK: selected: true
19registers:
20  - { id: 0, class: gprb }
21  - { id: 1, class: fprb }
22# CHECK: constants:
23# CHECK-NEXT: id: 0
24# CHECK-NEXT: value: 'float 0.000000e+00'
25# CHECK-NEXT: alignment: 4
26# CHECK-NEXT: isTargetSpecific: false
27body:             |
28  bb.0:
29    liveins: $r0
30
31    %0(p0) = COPY $r0
32    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
33
34    %1(s32) = G_FCONSTANT float 0.0
35    ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
36
37    G_STORE %1(s32), %0 :: (store 4)
38    ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
39
40    BX_RET 14, $noreg
41    ; CHECK: BX_RET 14 /* CC::al */, $noreg
42...
43---
44name:            test_fpconst_zero_s64
45# CHECK-LABEL: name: test_fpconst_zero_s64
46legalized:       true
47regBankSelected: true
48selected:        false
49# CHECK: selected: true
50registers:
51  - { id: 0, class: gprb }
52  - { id: 1, class: fprb }
53# CHECK: constants:
54# CHECK-NEXT: id: 0
55# CHECK-NEXT: value: 'double 0.000000e+00'
56# CHECK-NEXT: alignment: 8
57# CHECK-NEXT: isTargetSpecific: false
58body:             |
59  bb.0:
60    liveins: $r0
61
62    %0(p0) = COPY $r0
63    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
64
65    %1(s64) = G_FCONSTANT double 0.0
66    ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
67
68    G_STORE %1(s64), %0 :: (store 8)
69    ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
70
71    BX_RET 14, $noreg
72    ; CHECK: BX_RET 14 /* CC::al */, $noreg
73...
74---
75name:            test_fpconst_8bit_s32
76# CHECK-LABEL: name: test_fpconst_8bit_s32
77legalized:       true
78regBankSelected: true
79selected:        false
80# CHECK: selected: true
81registers:
82  - { id: 0, class: gprb }
83  - { id: 1, class: fprb }
84# VFP3: constants: []
85# VFP2: constants:
86# VFP2-NEXT: id: 0
87# VFP2-NEXT: value: 'float -2.000000e+00'
88# VFP2-NEXT: alignment: 4
89# VFP2-NEXT: isTargetSpecific: false
90body:             |
91  bb.0:
92    liveins: $r0
93
94    %0(p0) = COPY $r0
95    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
96
97    %1(s32) = G_FCONSTANT float -2.0
98    ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg
99    ; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
100
101    G_STORE %1(s32), %0 :: (store 4)
102    ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
103
104    BX_RET 14, $noreg
105    ; CHECK: BX_RET 14 /* CC::al */, $noreg
106...
107---
108name:            test_fpconst_8bit_s64
109# CHECK-LABEL: name: test_fpconst_8bit_s64
110legalized:       true
111regBankSelected: true
112selected:        false
113# CHECK: selected: true
114registers:
115  - { id: 0, class: gprb }
116  - { id: 1, class: fprb }
117# VFP3: constants: []
118# VFP2: constants:
119# VFP2-NEXT: id: 0
120# VFP2-NEXT: value: double 5.000000e-01
121# VFP2-NEXT: alignment: 8
122# VFP2-NEXT: isTargetSpecific: false
123body:             |
124  bb.0:
125    liveins: $r0
126
127    %0(p0) = COPY $r0
128    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
129
130    %1(s64) = G_FCONSTANT double 5.0e-1
131    ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 /* CC::al */, $noreg
132    ; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant-pool)
133
134    G_STORE %1(s64), %0 :: (store 8)
135    ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
136
137    BX_RET 14, $noreg
138    ; CHECK: BX_RET 14 /* CC::al */, $noreg
139...
140