1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s --check-prefix=ARM
3; RUN: llc -mtriple=armv7eb %s -o - | FileCheck %s --check-prefix=ARMEB
4; RUN: llc -mtriple=armv6m %s -o - | FileCheck %s --check-prefix=THUMB1
5; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
6
7define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a, i16* nocapture readonly %b) {
8; ARM-LABEL: cmp_xor8_short_short:
9; ARM:       @ %bb.0: @ %entry
10; ARM-NEXT:    ldrb r0, [r0]
11; ARM-NEXT:    ldrb r1, [r1]
12; ARM-NEXT:    eor r0, r1, r0
13; ARM-NEXT:    clz r0, r0
14; ARM-NEXT:    lsr r0, r0, #5
15; ARM-NEXT:    bx lr
16;
17; ARMEB-LABEL: cmp_xor8_short_short:
18; ARMEB:       @ %bb.0: @ %entry
19; ARMEB-NEXT:    ldrb r0, [r0, #1]
20; ARMEB-NEXT:    ldrb r1, [r1, #1]
21; ARMEB-NEXT:    eor r0, r1, r0
22; ARMEB-NEXT:    clz r0, r0
23; ARMEB-NEXT:    lsr r0, r0, #5
24; ARMEB-NEXT:    bx lr
25;
26; THUMB1-LABEL: cmp_xor8_short_short:
27; THUMB1:       @ %bb.0: @ %entry
28; THUMB1-NEXT:    ldrb r0, [r0]
29; THUMB1-NEXT:    ldrb r1, [r1]
30; THUMB1-NEXT:    eors r1, r0
31; THUMB1-NEXT:    rsbs r0, r1, #0
32; THUMB1-NEXT:    adcs r0, r1
33; THUMB1-NEXT:    bx lr
34;
35; THUMB2-LABEL: cmp_xor8_short_short:
36; THUMB2:       @ %bb.0: @ %entry
37; THUMB2-NEXT:    ldrb r0, [r0]
38; THUMB2-NEXT:    ldrb r1, [r1]
39; THUMB2-NEXT:    eors r0, r1
40; THUMB2-NEXT:    clz r0, r0
41; THUMB2-NEXT:    lsrs r0, r0, #5
42; THUMB2-NEXT:    bx lr
43entry:
44  %0 = load i16, i16* %a, align 2
45  %1 = load i16, i16* %b, align 2
46  %xor2 = xor i16 %1, %0
47  %2 = and i16 %xor2, 255
48  %cmp = icmp eq i16 %2, 0
49  ret i1 %cmp
50}
51
52define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
53; ARM-LABEL: cmp_xor8_short_int:
54; ARM:       @ %bb.0: @ %entry
55; ARM-NEXT:    ldrb r0, [r0]
56; ARM-NEXT:    ldrb r1, [r1]
57; ARM-NEXT:    eor r0, r1, r0
58; ARM-NEXT:    clz r0, r0
59; ARM-NEXT:    lsr r0, r0, #5
60; ARM-NEXT:    bx lr
61;
62; ARMEB-LABEL: cmp_xor8_short_int:
63; ARMEB:       @ %bb.0: @ %entry
64; ARMEB-NEXT:    ldrb r0, [r0, #1]
65; ARMEB-NEXT:    ldrb r1, [r1, #3]
66; ARMEB-NEXT:    eor r0, r1, r0
67; ARMEB-NEXT:    clz r0, r0
68; ARMEB-NEXT:    lsr r0, r0, #5
69; ARMEB-NEXT:    bx lr
70;
71; THUMB1-LABEL: cmp_xor8_short_int:
72; THUMB1:       @ %bb.0: @ %entry
73; THUMB1-NEXT:    ldrb r0, [r0]
74; THUMB1-NEXT:    ldrb r1, [r1]
75; THUMB1-NEXT:    eors r1, r0
76; THUMB1-NEXT:    rsbs r0, r1, #0
77; THUMB1-NEXT:    adcs r0, r1
78; THUMB1-NEXT:    bx lr
79;
80; THUMB2-LABEL: cmp_xor8_short_int:
81; THUMB2:       @ %bb.0: @ %entry
82; THUMB2-NEXT:    ldrb r0, [r0]
83; THUMB2-NEXT:    ldrb r1, [r1]
84; THUMB2-NEXT:    eors r0, r1
85; THUMB2-NEXT:    clz r0, r0
86; THUMB2-NEXT:    lsrs r0, r0, #5
87; THUMB2-NEXT:    bx lr
88entry:
89  %0 = load i16, i16* %a, align 2
90  %conv = zext i16 %0 to i32
91  %1 = load i32, i32* %b, align 4
92  %xor = xor i32 %1, %conv
93  %and = and i32 %xor, 255
94  %cmp = icmp eq i32 %and, 0
95  ret i1 %cmp
96}
97
98define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a, i32* nocapture readonly %b) {
99; ARM-LABEL: cmp_xor8_int_int:
100; ARM:       @ %bb.0: @ %entry
101; ARM-NEXT:    ldrb r0, [r0]
102; ARM-NEXT:    ldrb r1, [r1]
103; ARM-NEXT:    eor r0, r1, r0
104; ARM-NEXT:    clz r0, r0
105; ARM-NEXT:    lsr r0, r0, #5
106; ARM-NEXT:    bx lr
107;
108; ARMEB-LABEL: cmp_xor8_int_int:
109; ARMEB:       @ %bb.0: @ %entry
110; ARMEB-NEXT:    ldrb r0, [r0, #3]
111; ARMEB-NEXT:    ldrb r1, [r1, #3]
112; ARMEB-NEXT:    eor r0, r1, r0
113; ARMEB-NEXT:    clz r0, r0
114; ARMEB-NEXT:    lsr r0, r0, #5
115; ARMEB-NEXT:    bx lr
116;
117; THUMB1-LABEL: cmp_xor8_int_int:
118; THUMB1:       @ %bb.0: @ %entry
119; THUMB1-NEXT:    ldrb r0, [r0]
120; THUMB1-NEXT:    ldrb r1, [r1]
121; THUMB1-NEXT:    eors r1, r0
122; THUMB1-NEXT:    rsbs r0, r1, #0
123; THUMB1-NEXT:    adcs r0, r1
124; THUMB1-NEXT:    bx lr
125;
126; THUMB2-LABEL: cmp_xor8_int_int:
127; THUMB2:       @ %bb.0: @ %entry
128; THUMB2-NEXT:    ldrb r0, [r0]
129; THUMB2-NEXT:    ldrb r1, [r1]
130; THUMB2-NEXT:    eors r0, r1
131; THUMB2-NEXT:    clz r0, r0
132; THUMB2-NEXT:    lsrs r0, r0, #5
133; THUMB2-NEXT:    bx lr
134entry:
135  %0 = load i32, i32* %a, align 4
136  %1 = load i32, i32* %b, align 4
137  %xor = xor i32 %1, %0
138  %and = and i32 %xor, 255
139  %cmp = icmp eq i32 %and, 0
140  ret i1 %cmp
141}
142
143define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a, i32* nocapture readonly %b) {
144; ARM-LABEL: cmp_xor16:
145; ARM:       @ %bb.0: @ %entry
146; ARM-NEXT:    ldrh r0, [r0]
147; ARM-NEXT:    ldrh r1, [r1]
148; ARM-NEXT:    eor r0, r1, r0
149; ARM-NEXT:    clz r0, r0
150; ARM-NEXT:    lsr r0, r0, #5
151; ARM-NEXT:    bx lr
152;
153; ARMEB-LABEL: cmp_xor16:
154; ARMEB:       @ %bb.0: @ %entry
155; ARMEB-NEXT:    ldrh r0, [r0, #2]
156; ARMEB-NEXT:    ldrh r1, [r1, #2]
157; ARMEB-NEXT:    eor r0, r1, r0
158; ARMEB-NEXT:    clz r0, r0
159; ARMEB-NEXT:    lsr r0, r0, #5
160; ARMEB-NEXT:    bx lr
161;
162; THUMB1-LABEL: cmp_xor16:
163; THUMB1:       @ %bb.0: @ %entry
164; THUMB1-NEXT:    ldrh r0, [r0]
165; THUMB1-NEXT:    ldrh r1, [r1]
166; THUMB1-NEXT:    eors r1, r0
167; THUMB1-NEXT:    rsbs r0, r1, #0
168; THUMB1-NEXT:    adcs r0, r1
169; THUMB1-NEXT:    bx lr
170;
171; THUMB2-LABEL: cmp_xor16:
172; THUMB2:       @ %bb.0: @ %entry
173; THUMB2-NEXT:    ldrh r0, [r0]
174; THUMB2-NEXT:    ldrh r1, [r1]
175; THUMB2-NEXT:    eors r0, r1
176; THUMB2-NEXT:    clz r0, r0
177; THUMB2-NEXT:    lsrs r0, r0, #5
178; THUMB2-NEXT:    bx lr
179entry:
180  %0 = load i32, i32* %a, align 4
181  %1 = load i32, i32* %b, align 4
182  %xor = xor i32 %1, %0
183  %and = and i32 %xor, 65535
184  %cmp = icmp eq i32 %and, 0
185  ret i1 %cmp
186}
187
188define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a, i16* nocapture readonly %b) {
189; ARM-LABEL: cmp_or8_short_short:
190; ARM:       @ %bb.0: @ %entry
191; ARM-NEXT:    ldrb r0, [r0]
192; ARM-NEXT:    ldrb r1, [r1]
193; ARM-NEXT:    orr r0, r1, r0
194; ARM-NEXT:    clz r0, r0
195; ARM-NEXT:    lsr r0, r0, #5
196; ARM-NEXT:    bx lr
197;
198; ARMEB-LABEL: cmp_or8_short_short:
199; ARMEB:       @ %bb.0: @ %entry
200; ARMEB-NEXT:    ldrb r0, [r0, #1]
201; ARMEB-NEXT:    ldrb r1, [r1, #1]
202; ARMEB-NEXT:    orr r0, r1, r0
203; ARMEB-NEXT:    clz r0, r0
204; ARMEB-NEXT:    lsr r0, r0, #5
205; ARMEB-NEXT:    bx lr
206;
207; THUMB1-LABEL: cmp_or8_short_short:
208; THUMB1:       @ %bb.0: @ %entry
209; THUMB1-NEXT:    ldrb r0, [r0]
210; THUMB1-NEXT:    ldrb r1, [r1]
211; THUMB1-NEXT:    orrs r1, r0
212; THUMB1-NEXT:    rsbs r0, r1, #0
213; THUMB1-NEXT:    adcs r0, r1
214; THUMB1-NEXT:    bx lr
215;
216; THUMB2-LABEL: cmp_or8_short_short:
217; THUMB2:       @ %bb.0: @ %entry
218; THUMB2-NEXT:    ldrb r0, [r0]
219; THUMB2-NEXT:    ldrb r1, [r1]
220; THUMB2-NEXT:    orrs r0, r1
221; THUMB2-NEXT:    clz r0, r0
222; THUMB2-NEXT:    lsrs r0, r0, #5
223; THUMB2-NEXT:    bx lr
224entry:
225  %0 = load i16, i16* %a, align 2
226  %1 = load i16, i16* %b, align 2
227  %or2 = or i16 %1, %0
228  %2 = and i16 %or2, 255
229  %cmp = icmp eq i16 %2, 0
230  ret i1 %cmp
231}
232
233define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
234; ARM-LABEL: cmp_or8_short_int:
235; ARM:       @ %bb.0: @ %entry
236; ARM-NEXT:    ldrb r0, [r0]
237; ARM-NEXT:    ldrb r1, [r1]
238; ARM-NEXT:    orr r0, r1, r0
239; ARM-NEXT:    clz r0, r0
240; ARM-NEXT:    lsr r0, r0, #5
241; ARM-NEXT:    bx lr
242;
243; ARMEB-LABEL: cmp_or8_short_int:
244; ARMEB:       @ %bb.0: @ %entry
245; ARMEB-NEXT:    ldrb r0, [r0, #1]
246; ARMEB-NEXT:    ldrb r1, [r1, #3]
247; ARMEB-NEXT:    orr r0, r1, r0
248; ARMEB-NEXT:    clz r0, r0
249; ARMEB-NEXT:    lsr r0, r0, #5
250; ARMEB-NEXT:    bx lr
251;
252; THUMB1-LABEL: cmp_or8_short_int:
253; THUMB1:       @ %bb.0: @ %entry
254; THUMB1-NEXT:    ldrb r0, [r0]
255; THUMB1-NEXT:    ldrb r1, [r1]
256; THUMB1-NEXT:    orrs r1, r0
257; THUMB1-NEXT:    rsbs r0, r1, #0
258; THUMB1-NEXT:    adcs r0, r1
259; THUMB1-NEXT:    bx lr
260;
261; THUMB2-LABEL: cmp_or8_short_int:
262; THUMB2:       @ %bb.0: @ %entry
263; THUMB2-NEXT:    ldrb r0, [r0]
264; THUMB2-NEXT:    ldrb r1, [r1]
265; THUMB2-NEXT:    orrs r0, r1
266; THUMB2-NEXT:    clz r0, r0
267; THUMB2-NEXT:    lsrs r0, r0, #5
268; THUMB2-NEXT:    bx lr
269entry:
270  %0 = load i16, i16* %a, align 2
271  %conv = zext i16 %0 to i32
272  %1 = load i32, i32* %b, align 4
273  %or = or i32 %1, %conv
274  %and = and i32 %or, 255
275  %cmp = icmp eq i32 %and, 0
276  ret i1 %cmp
277}
278
279define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a, i32* nocapture readonly %b) {
280; ARM-LABEL: cmp_or8_int_int:
281; ARM:       @ %bb.0: @ %entry
282; ARM-NEXT:    ldrb r0, [r0]
283; ARM-NEXT:    ldrb r1, [r1]
284; ARM-NEXT:    orr r0, r1, r0
285; ARM-NEXT:    clz r0, r0
286; ARM-NEXT:    lsr r0, r0, #5
287; ARM-NEXT:    bx lr
288;
289; ARMEB-LABEL: cmp_or8_int_int:
290; ARMEB:       @ %bb.0: @ %entry
291; ARMEB-NEXT:    ldrb r0, [r0, #3]
292; ARMEB-NEXT:    ldrb r1, [r1, #3]
293; ARMEB-NEXT:    orr r0, r1, r0
294; ARMEB-NEXT:    clz r0, r0
295; ARMEB-NEXT:    lsr r0, r0, #5
296; ARMEB-NEXT:    bx lr
297;
298; THUMB1-LABEL: cmp_or8_int_int:
299; THUMB1:       @ %bb.0: @ %entry
300; THUMB1-NEXT:    ldrb r0, [r0]
301; THUMB1-NEXT:    ldrb r1, [r1]
302; THUMB1-NEXT:    orrs r1, r0
303; THUMB1-NEXT:    rsbs r0, r1, #0
304; THUMB1-NEXT:    adcs r0, r1
305; THUMB1-NEXT:    bx lr
306;
307; THUMB2-LABEL: cmp_or8_int_int:
308; THUMB2:       @ %bb.0: @ %entry
309; THUMB2-NEXT:    ldrb r0, [r0]
310; THUMB2-NEXT:    ldrb r1, [r1]
311; THUMB2-NEXT:    orrs r0, r1
312; THUMB2-NEXT:    clz r0, r0
313; THUMB2-NEXT:    lsrs r0, r0, #5
314; THUMB2-NEXT:    bx lr
315entry:
316  %0 = load i32, i32* %a, align 4
317  %1 = load i32, i32* %b, align 4
318  %or = or i32 %1, %0
319  %and = and i32 %or, 255
320  %cmp = icmp eq i32 %and, 0
321  ret i1 %cmp
322}
323
324define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a, i32* nocapture readonly %b) {
325; ARM-LABEL: cmp_or16:
326; ARM:       @ %bb.0: @ %entry
327; ARM-NEXT:    ldrh r0, [r0]
328; ARM-NEXT:    ldrh r1, [r1]
329; ARM-NEXT:    orr r0, r1, r0
330; ARM-NEXT:    clz r0, r0
331; ARM-NEXT:    lsr r0, r0, #5
332; ARM-NEXT:    bx lr
333;
334; ARMEB-LABEL: cmp_or16:
335; ARMEB:       @ %bb.0: @ %entry
336; ARMEB-NEXT:    ldrh r0, [r0, #2]
337; ARMEB-NEXT:    ldrh r1, [r1, #2]
338; ARMEB-NEXT:    orr r0, r1, r0
339; ARMEB-NEXT:    clz r0, r0
340; ARMEB-NEXT:    lsr r0, r0, #5
341; ARMEB-NEXT:    bx lr
342;
343; THUMB1-LABEL: cmp_or16:
344; THUMB1:       @ %bb.0: @ %entry
345; THUMB1-NEXT:    ldrh r0, [r0]
346; THUMB1-NEXT:    ldrh r1, [r1]
347; THUMB1-NEXT:    orrs r1, r0
348; THUMB1-NEXT:    rsbs r0, r1, #0
349; THUMB1-NEXT:    adcs r0, r1
350; THUMB1-NEXT:    bx lr
351;
352; THUMB2-LABEL: cmp_or16:
353; THUMB2:       @ %bb.0: @ %entry
354; THUMB2-NEXT:    ldrh r0, [r0]
355; THUMB2-NEXT:    ldrh r1, [r1]
356; THUMB2-NEXT:    orrs r0, r1
357; THUMB2-NEXT:    clz r0, r0
358; THUMB2-NEXT:    lsrs r0, r0, #5
359; THUMB2-NEXT:    bx lr
360entry:
361  %0 = load i32, i32* %a, align 4
362  %1 = load i32, i32* %b, align 4
363  %or = or i32 %1, %0
364  %and = and i32 %or, 65535
365  %cmp = icmp eq i32 %and, 0
366  ret i1 %cmp
367}
368
369define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a, i16* nocapture readonly %b) {
370; ARM-LABEL: cmp_and8_short_short:
371; ARM:       @ %bb.0: @ %entry
372; ARM-NEXT:    ldrb r1, [r1]
373; ARM-NEXT:    ldrb r0, [r0]
374; ARM-NEXT:    and r0, r0, r1
375; ARM-NEXT:    clz r0, r0
376; ARM-NEXT:    lsr r0, r0, #5
377; ARM-NEXT:    bx lr
378;
379; ARMEB-LABEL: cmp_and8_short_short:
380; ARMEB:       @ %bb.0: @ %entry
381; ARMEB-NEXT:    ldrb r1, [r1, #1]
382; ARMEB-NEXT:    ldrb r0, [r0, #1]
383; ARMEB-NEXT:    and r0, r0, r1
384; ARMEB-NEXT:    clz r0, r0
385; ARMEB-NEXT:    lsr r0, r0, #5
386; ARMEB-NEXT:    bx lr
387;
388; THUMB1-LABEL: cmp_and8_short_short:
389; THUMB1:       @ %bb.0: @ %entry
390; THUMB1-NEXT:    ldrb r1, [r1]
391; THUMB1-NEXT:    ldrb r2, [r0]
392; THUMB1-NEXT:    ands r2, r1
393; THUMB1-NEXT:    rsbs r0, r2, #0
394; THUMB1-NEXT:    adcs r0, r2
395; THUMB1-NEXT:    bx lr
396;
397; THUMB2-LABEL: cmp_and8_short_short:
398; THUMB2:       @ %bb.0: @ %entry
399; THUMB2-NEXT:    ldrb r1, [r1]
400; THUMB2-NEXT:    ldrb r0, [r0]
401; THUMB2-NEXT:    ands r0, r1
402; THUMB2-NEXT:    clz r0, r0
403; THUMB2-NEXT:    lsrs r0, r0, #5
404; THUMB2-NEXT:    bx lr
405entry:
406  %0 = load i16, i16* %a, align 2
407  %1 = load i16, i16* %b, align 2
408  %and3 = and i16 %0, 255
409  %2 = and i16 %and3, %1
410  %cmp = icmp eq i16 %2, 0
411  ret i1 %cmp
412}
413
414define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
415; ARM-LABEL: cmp_and8_short_int:
416; ARM:       @ %bb.0: @ %entry
417; ARM-NEXT:    ldrb r1, [r1]
418; ARM-NEXT:    ldrb r0, [r0]
419; ARM-NEXT:    and r0, r0, r1
420; ARM-NEXT:    clz r0, r0
421; ARM-NEXT:    lsr r0, r0, #5
422; ARM-NEXT:    bx lr
423;
424; ARMEB-LABEL: cmp_and8_short_int:
425; ARMEB:       @ %bb.0: @ %entry
426; ARMEB-NEXT:    ldrb r1, [r1, #3]
427; ARMEB-NEXT:    ldrb r0, [r0, #1]
428; ARMEB-NEXT:    and r0, r0, r1
429; ARMEB-NEXT:    clz r0, r0
430; ARMEB-NEXT:    lsr r0, r0, #5
431; ARMEB-NEXT:    bx lr
432;
433; THUMB1-LABEL: cmp_and8_short_int:
434; THUMB1:       @ %bb.0: @ %entry
435; THUMB1-NEXT:    ldrb r1, [r1]
436; THUMB1-NEXT:    ldrb r2, [r0]
437; THUMB1-NEXT:    ands r2, r1
438; THUMB1-NEXT:    rsbs r0, r2, #0
439; THUMB1-NEXT:    adcs r0, r2
440; THUMB1-NEXT:    bx lr
441;
442; THUMB2-LABEL: cmp_and8_short_int:
443; THUMB2:       @ %bb.0: @ %entry
444; THUMB2-NEXT:    ldrb r1, [r1]
445; THUMB2-NEXT:    ldrb r0, [r0]
446; THUMB2-NEXT:    ands r0, r1
447; THUMB2-NEXT:    clz r0, r0
448; THUMB2-NEXT:    lsrs r0, r0, #5
449; THUMB2-NEXT:    bx lr
450entry:
451  %0 = load i16, i16* %a, align 2
452  %1 = load i32, i32* %b, align 4
453  %2 = and i16 %0, 255
454  %and = zext i16 %2 to i32
455  %and1 = and i32 %1, %and
456  %cmp = icmp eq i32 %and1, 0
457  ret i1 %cmp
458}
459
460define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a, i32* nocapture readonly %b) {
461; ARM-LABEL: cmp_and8_int_int:
462; ARM:       @ %bb.0: @ %entry
463; ARM-NEXT:    ldrb r1, [r1]
464; ARM-NEXT:    ldrb r0, [r0]
465; ARM-NEXT:    and r0, r0, r1
466; ARM-NEXT:    clz r0, r0
467; ARM-NEXT:    lsr r0, r0, #5
468; ARM-NEXT:    bx lr
469;
470; ARMEB-LABEL: cmp_and8_int_int:
471; ARMEB:       @ %bb.0: @ %entry
472; ARMEB-NEXT:    ldrb r1, [r1, #3]
473; ARMEB-NEXT:    ldrb r0, [r0, #3]
474; ARMEB-NEXT:    and r0, r0, r1
475; ARMEB-NEXT:    clz r0, r0
476; ARMEB-NEXT:    lsr r0, r0, #5
477; ARMEB-NEXT:    bx lr
478;
479; THUMB1-LABEL: cmp_and8_int_int:
480; THUMB1:       @ %bb.0: @ %entry
481; THUMB1-NEXT:    ldrb r1, [r1]
482; THUMB1-NEXT:    ldrb r2, [r0]
483; THUMB1-NEXT:    ands r2, r1
484; THUMB1-NEXT:    rsbs r0, r2, #0
485; THUMB1-NEXT:    adcs r0, r2
486; THUMB1-NEXT:    bx lr
487;
488; THUMB2-LABEL: cmp_and8_int_int:
489; THUMB2:       @ %bb.0: @ %entry
490; THUMB2-NEXT:    ldrb r1, [r1]
491; THUMB2-NEXT:    ldrb r0, [r0]
492; THUMB2-NEXT:    ands r0, r1
493; THUMB2-NEXT:    clz r0, r0
494; THUMB2-NEXT:    lsrs r0, r0, #5
495; THUMB2-NEXT:    bx lr
496entry:
497  %0 = load i32, i32* %a, align 4
498  %1 = load i32, i32* %b, align 4
499  %and = and i32 %0, 255
500  %and1 = and i32 %and, %1
501  %cmp = icmp eq i32 %and1, 0
502  ret i1 %cmp
503}
504
505define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a, i32* nocapture readonly %b) {
506; ARM-LABEL: cmp_and16:
507; ARM:       @ %bb.0: @ %entry
508; ARM-NEXT:    ldrh r1, [r1]
509; ARM-NEXT:    ldrh r0, [r0]
510; ARM-NEXT:    and r0, r0, r1
511; ARM-NEXT:    clz r0, r0
512; ARM-NEXT:    lsr r0, r0, #5
513; ARM-NEXT:    bx lr
514;
515; ARMEB-LABEL: cmp_and16:
516; ARMEB:       @ %bb.0: @ %entry
517; ARMEB-NEXT:    ldrh r1, [r1, #2]
518; ARMEB-NEXT:    ldrh r0, [r0, #2]
519; ARMEB-NEXT:    and r0, r0, r1
520; ARMEB-NEXT:    clz r0, r0
521; ARMEB-NEXT:    lsr r0, r0, #5
522; ARMEB-NEXT:    bx lr
523;
524; THUMB1-LABEL: cmp_and16:
525; THUMB1:       @ %bb.0: @ %entry
526; THUMB1-NEXT:    ldrh r1, [r1]
527; THUMB1-NEXT:    ldrh r2, [r0]
528; THUMB1-NEXT:    ands r2, r1
529; THUMB1-NEXT:    rsbs r0, r2, #0
530; THUMB1-NEXT:    adcs r0, r2
531; THUMB1-NEXT:    bx lr
532;
533; THUMB2-LABEL: cmp_and16:
534; THUMB2:       @ %bb.0: @ %entry
535; THUMB2-NEXT:    ldrh r1, [r1]
536; THUMB2-NEXT:    ldrh r0, [r0]
537; THUMB2-NEXT:    ands r0, r1
538; THUMB2-NEXT:    clz r0, r0
539; THUMB2-NEXT:    lsrs r0, r0, #5
540; THUMB2-NEXT:    bx lr
541entry:
542  %0 = load i32, i32* %a, align 4
543  %1 = load i32, i32* %b, align 4
544  %and = and i32 %0, 65535
545  %and1 = and i32 %and, %1
546  %cmp = icmp eq i32 %and1, 0
547  ret i1 %cmp
548}
549
550define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
551; ARM-LABEL: add_and16:
552; ARM:       @ %bb.0: @ %entry
553; ARM-NEXT:    add r1, r1, r2
554; ARM-NEXT:    ldrh r0, [r0]
555; ARM-NEXT:    uxth r1, r1
556; ARM-NEXT:    orr r0, r0, r1
557; ARM-NEXT:    bx lr
558;
559; ARMEB-LABEL: add_and16:
560; ARMEB:       @ %bb.0: @ %entry
561; ARMEB-NEXT:    add r1, r1, r2
562; ARMEB-NEXT:    ldrh r0, [r0, #2]
563; ARMEB-NEXT:    uxth r1, r1
564; ARMEB-NEXT:    orr r0, r0, r1
565; ARMEB-NEXT:    bx lr
566;
567; THUMB1-LABEL: add_and16:
568; THUMB1:       @ %bb.0: @ %entry
569; THUMB1-NEXT:    adds r1, r1, r2
570; THUMB1-NEXT:    uxth r1, r1
571; THUMB1-NEXT:    ldrh r0, [r0]
572; THUMB1-NEXT:    orrs r0, r1
573; THUMB1-NEXT:    bx lr
574;
575; THUMB2-LABEL: add_and16:
576; THUMB2:       @ %bb.0: @ %entry
577; THUMB2-NEXT:    add r1, r2
578; THUMB2-NEXT:    ldrh r0, [r0]
579; THUMB2-NEXT:    uxth r1, r1
580; THUMB2-NEXT:    orrs r0, r1
581; THUMB2-NEXT:    bx lr
582entry:
583  %x = load i32, i32* %a, align 4
584  %add = add i32 %y, %z
585  %or = or i32 %x, %add
586  %and = and i32 %or, 65535
587  ret i32 %and
588}
589
590define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
591; ARM-LABEL: test1:
592; ARM:       @ %bb.0: @ %entry
593; ARM-NEXT:    mul r2, r2, r3
594; ARM-NEXT:    ldrh r1, [r1]
595; ARM-NEXT:    ldrh r0, [r0]
596; ARM-NEXT:    eor r0, r0, r1
597; ARM-NEXT:    uxth r1, r2
598; ARM-NEXT:    orr r0, r0, r1
599; ARM-NEXT:    bx lr
600;
601; ARMEB-LABEL: test1:
602; ARMEB:       @ %bb.0: @ %entry
603; ARMEB-NEXT:    mul r2, r2, r3
604; ARMEB-NEXT:    ldrh r1, [r1, #2]
605; ARMEB-NEXT:    ldrh r0, [r0, #2]
606; ARMEB-NEXT:    eor r0, r0, r1
607; ARMEB-NEXT:    uxth r1, r2
608; ARMEB-NEXT:    orr r0, r0, r1
609; ARMEB-NEXT:    bx lr
610;
611; THUMB1-LABEL: test1:
612; THUMB1:       @ %bb.0: @ %entry
613; THUMB1-NEXT:    push {r4, lr}
614; THUMB1-NEXT:    ldrh r1, [r1]
615; THUMB1-NEXT:    ldrh r4, [r0]
616; THUMB1-NEXT:    eors r4, r1
617; THUMB1-NEXT:    muls r2, r3, r2
618; THUMB1-NEXT:    uxth r0, r2
619; THUMB1-NEXT:    orrs r0, r4
620; THUMB1-NEXT:    pop {r4, pc}
621;
622; THUMB2-LABEL: test1:
623; THUMB2:       @ %bb.0: @ %entry
624; THUMB2-NEXT:    ldrh r1, [r1]
625; THUMB2-NEXT:    ldrh r0, [r0]
626; THUMB2-NEXT:    eors r0, r1
627; THUMB2-NEXT:    mul r1, r2, r3
628; THUMB2-NEXT:    uxth r1, r1
629; THUMB2-NEXT:    orrs r0, r1
630; THUMB2-NEXT:    bx lr
631entry:
632  %0 = load i32, i32* %a, align 4
633  %1 = load i32, i32* %b, align 4
634  %mul = mul i32 %x, %y
635  %xor = xor i32 %0, %1
636  %or = or i32 %xor, %mul
637  %and = and i32 %or, 65535
638  ret i32 %and
639}
640
641define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
642; ARM-LABEL: test2:
643; ARM:       @ %bb.0: @ %entry
644; ARM-NEXT:    ldr r1, [r1]
645; ARM-NEXT:    ldr r0, [r0]
646; ARM-NEXT:    mul r1, r2, r1
647; ARM-NEXT:    eor r0, r0, r3
648; ARM-NEXT:    orr r0, r0, r1
649; ARM-NEXT:    uxth r0, r0
650; ARM-NEXT:    bx lr
651;
652; ARMEB-LABEL: test2:
653; ARMEB:       @ %bb.0: @ %entry
654; ARMEB-NEXT:    ldr r1, [r1]
655; ARMEB-NEXT:    ldr r0, [r0]
656; ARMEB-NEXT:    mul r1, r2, r1
657; ARMEB-NEXT:    eor r0, r0, r3
658; ARMEB-NEXT:    orr r0, r0, r1
659; ARMEB-NEXT:    uxth r0, r0
660; ARMEB-NEXT:    bx lr
661;
662; THUMB1-LABEL: test2:
663; THUMB1:       @ %bb.0: @ %entry
664; THUMB1-NEXT:    ldr r1, [r1]
665; THUMB1-NEXT:    muls r1, r2, r1
666; THUMB1-NEXT:    ldr r0, [r0]
667; THUMB1-NEXT:    eors r0, r3
668; THUMB1-NEXT:    orrs r0, r1
669; THUMB1-NEXT:    uxth r0, r0
670; THUMB1-NEXT:    bx lr
671;
672; THUMB2-LABEL: test2:
673; THUMB2:       @ %bb.0: @ %entry
674; THUMB2-NEXT:    ldr r1, [r1]
675; THUMB2-NEXT:    ldr r0, [r0]
676; THUMB2-NEXT:    muls r1, r2, r1
677; THUMB2-NEXT:    eors r0, r3
678; THUMB2-NEXT:    orrs r0, r1
679; THUMB2-NEXT:    uxth r0, r0
680; THUMB2-NEXT:    bx lr
681entry:
682  %0 = load i32, i32* %a, align 4
683  %1 = load i32, i32* %b, align 4
684  %mul = mul i32 %x, %1
685  %xor = xor i32 %0, %y
686  %or = or i32 %xor, %mul
687  %and = and i32 %or, 65535
688  ret i32 %and
689}
690
691define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
692; ARM-LABEL: test3:
693; ARM:       @ %bb.0: @ %entry
694; ARM-NEXT:    ldr r0, [r0]
695; ARM-NEXT:    mul r1, r2, r0
696; ARM-NEXT:    ldrh r2, [r3]
697; ARM-NEXT:    eor r0, r0, r2
698; ARM-NEXT:    orr r0, r0, r1
699; ARM-NEXT:    uxth r0, r0
700; ARM-NEXT:    bx lr
701;
702; ARMEB-LABEL: test3:
703; ARMEB:       @ %bb.0: @ %entry
704; ARMEB-NEXT:    ldr r0, [r0]
705; ARMEB-NEXT:    mul r1, r2, r0
706; ARMEB-NEXT:    ldrh r2, [r3]
707; ARMEB-NEXT:    eor r0, r0, r2
708; ARMEB-NEXT:    orr r0, r0, r1
709; ARMEB-NEXT:    uxth r0, r0
710; ARMEB-NEXT:    bx lr
711;
712; THUMB1-LABEL: test3:
713; THUMB1:       @ %bb.0: @ %entry
714; THUMB1-NEXT:    ldr r0, [r0]
715; THUMB1-NEXT:    muls r2, r0, r2
716; THUMB1-NEXT:    ldrh r1, [r3]
717; THUMB1-NEXT:    eors r1, r0
718; THUMB1-NEXT:    orrs r1, r2
719; THUMB1-NEXT:    uxth r0, r1
720; THUMB1-NEXT:    bx lr
721;
722; THUMB2-LABEL: test3:
723; THUMB2:       @ %bb.0: @ %entry
724; THUMB2-NEXT:    ldr r0, [r0]
725; THUMB2-NEXT:    mul r1, r2, r0
726; THUMB2-NEXT:    ldrh r2, [r3]
727; THUMB2-NEXT:    eors r0, r2
728; THUMB2-NEXT:    orrs r0, r1
729; THUMB2-NEXT:    uxth r0, r0
730; THUMB2-NEXT:    bx lr
731entry:
732  %0 = load i32, i32* %a, align 4
733  %1 = load i16, i16* %y, align 4
734  %2 = zext i16 %1 to i32
735  %mul = mul i32 %x, %0
736  %xor = xor i32 %0, %2
737  %or = or i32 %xor, %mul
738  %and = and i32 %or, 65535
739  ret i32 %and
740}
741
742define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
743; ARM-LABEL: test4:
744; ARM:       @ %bb.0: @ %entry
745; ARM-NEXT:    mul r2, r2, r3
746; ARM-NEXT:    ldrh r1, [r1]
747; ARM-NEXT:    ldrh r0, [r0]
748; ARM-NEXT:    eor r0, r0, r1
749; ARM-NEXT:    uxth r1, r2
750; ARM-NEXT:    orr r0, r0, r1
751; ARM-NEXT:    bx lr
752;
753; ARMEB-LABEL: test4:
754; ARMEB:       @ %bb.0: @ %entry
755; ARMEB-NEXT:    mul r2, r2, r3
756; ARMEB-NEXT:    ldrh r1, [r1, #2]
757; ARMEB-NEXT:    ldrh r0, [r0, #2]
758; ARMEB-NEXT:    eor r0, r0, r1
759; ARMEB-NEXT:    uxth r1, r2
760; ARMEB-NEXT:    orr r0, r0, r1
761; ARMEB-NEXT:    bx lr
762;
763; THUMB1-LABEL: test4:
764; THUMB1:       @ %bb.0: @ %entry
765; THUMB1-NEXT:    push {r4, lr}
766; THUMB1-NEXT:    ldrh r1, [r1]
767; THUMB1-NEXT:    ldrh r4, [r0]
768; THUMB1-NEXT:    eors r4, r1
769; THUMB1-NEXT:    muls r2, r3, r2
770; THUMB1-NEXT:    uxth r0, r2
771; THUMB1-NEXT:    orrs r0, r4
772; THUMB1-NEXT:    pop {r4, pc}
773;
774; THUMB2-LABEL: test4:
775; THUMB2:       @ %bb.0: @ %entry
776; THUMB2-NEXT:    ldrh r1, [r1]
777; THUMB2-NEXT:    ldrh r0, [r0]
778; THUMB2-NEXT:    eors r0, r1
779; THUMB2-NEXT:    mul r1, r2, r3
780; THUMB2-NEXT:    uxth r1, r1
781; THUMB2-NEXT:    orrs r0, r1
782; THUMB2-NEXT:    bx lr
783entry:
784  %0 = load i32, i32* %a, align 4
785  %1 = load i32, i32* %b, align 4
786  %mul = mul i32 %x, %y
787  %xor = xor i32 %0, %1
788  %or = or i32 %xor, %mul
789  %and = and i32 %or, 65535
790  ret i32 %and
791}
792
793define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
794; ARM-LABEL: test5:
795; ARM:       @ %bb.0: @ %entry
796; ARM-NEXT:    ldr r1, [r1]
797; ARM-NEXT:    ldrh r0, [r0]
798; ARM-NEXT:    mul r1, r2, r1
799; ARM-NEXT:    eor r0, r0, r3
800; ARM-NEXT:    uxth r1, r1
801; ARM-NEXT:    orr r0, r0, r1
802; ARM-NEXT:    bx lr
803;
804; ARMEB-LABEL: test5:
805; ARMEB:       @ %bb.0: @ %entry
806; ARMEB-NEXT:    ldr r1, [r1]
807; ARMEB-NEXT:    ldrh r0, [r0, #2]
808; ARMEB-NEXT:    mul r1, r2, r1
809; ARMEB-NEXT:    eor r0, r0, r3
810; ARMEB-NEXT:    uxth r1, r1
811; ARMEB-NEXT:    orr r0, r0, r1
812; ARMEB-NEXT:    bx lr
813;
814; THUMB1-LABEL: test5:
815; THUMB1:       @ %bb.0: @ %entry
816; THUMB1-NEXT:    push {r4, lr}
817; THUMB1-NEXT:    ldrh r4, [r0]
818; THUMB1-NEXT:    eors r4, r3
819; THUMB1-NEXT:    ldr r0, [r1]
820; THUMB1-NEXT:    muls r0, r2, r0
821; THUMB1-NEXT:    uxth r0, r0
822; THUMB1-NEXT:    orrs r0, r4
823; THUMB1-NEXT:    pop {r4, pc}
824;
825; THUMB2-LABEL: test5:
826; THUMB2:       @ %bb.0: @ %entry
827; THUMB2-NEXT:    ldr r1, [r1]
828; THUMB2-NEXT:    ldrh r0, [r0]
829; THUMB2-NEXT:    muls r1, r2, r1
830; THUMB2-NEXT:    eors r0, r3
831; THUMB2-NEXT:    uxth r1, r1
832; THUMB2-NEXT:    orrs r0, r1
833; THUMB2-NEXT:    bx lr
834entry:
835  %0 = load i32, i32* %a, align 4
836  %1 = load i32, i32* %b, align 4
837  %mul = mul i32 %x, %1
838  %ext = zext i16 %y to i32
839  %xor = xor i32 %0, %ext
840  %or = or i32 %xor, %mul
841  %and = and i32 %or, 65535
842  ret i32 %and
843}
844
845define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
846; ARM-LABEL: test6:
847; ARM:       @ %bb.0: @ %entry
848; ARM-NEXT:    ldrb r0, [r0]
849; ARM-NEXT:    and r0, r1, r0
850; ARM-NEXT:    uxtb r1, r2
851; ARM-NEXT:    sub r0, r0, r1
852; ARM-NEXT:    clz r0, r0
853; ARM-NEXT:    lsr r0, r0, #5
854; ARM-NEXT:    bx lr
855;
856; ARMEB-LABEL: test6:
857; ARMEB:       @ %bb.0: @ %entry
858; ARMEB-NEXT:    ldrb r0, [r0]
859; ARMEB-NEXT:    and r0, r1, r0
860; ARMEB-NEXT:    uxtb r1, r2
861; ARMEB-NEXT:    sub r0, r0, r1
862; ARMEB-NEXT:    clz r0, r0
863; ARMEB-NEXT:    lsr r0, r0, #5
864; ARMEB-NEXT:    bx lr
865;
866; THUMB1-LABEL: test6:
867; THUMB1:       @ %bb.0: @ %entry
868; THUMB1-NEXT:    ldrb r0, [r0]
869; THUMB1-NEXT:    ands r0, r1
870; THUMB1-NEXT:    uxtb r1, r2
871; THUMB1-NEXT:    subs r1, r0, r1
872; THUMB1-NEXT:    rsbs r0, r1, #0
873; THUMB1-NEXT:    adcs r0, r1
874; THUMB1-NEXT:    bx lr
875;
876; THUMB2-LABEL: test6:
877; THUMB2:       @ %bb.0: @ %entry
878; THUMB2-NEXT:    ldrb r0, [r0]
879; THUMB2-NEXT:    ands r0, r1
880; THUMB2-NEXT:    uxtb r1, r2
881; THUMB2-NEXT:    subs r0, r0, r1
882; THUMB2-NEXT:    clz r0, r0
883; THUMB2-NEXT:    lsrs r0, r0, #5
884; THUMB2-NEXT:    bx lr
885entry:
886  %0 = load i8, i8* %x, align 4
887  %1 = and i8 %0, %y
888  %2 = icmp eq i8 %1, %z
889  ret i1 %2
890}
891
892define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
893; ARM-LABEL: test7:
894; ARM:       @ %bb.0: @ %entry
895; ARM-NEXT:    ldrb r0, [r0]
896; ARM-NEXT:    and r0, r1, r0
897; ARM-NEXT:    uxtb r1, r2
898; ARM-NEXT:    sub r0, r0, r1
899; ARM-NEXT:    clz r0, r0
900; ARM-NEXT:    lsr r0, r0, #5
901; ARM-NEXT:    bx lr
902;
903; ARMEB-LABEL: test7:
904; ARMEB:       @ %bb.0: @ %entry
905; ARMEB-NEXT:    ldrb r0, [r0, #1]
906; ARMEB-NEXT:    and r0, r1, r0
907; ARMEB-NEXT:    uxtb r1, r2
908; ARMEB-NEXT:    sub r0, r0, r1
909; ARMEB-NEXT:    clz r0, r0
910; ARMEB-NEXT:    lsr r0, r0, #5
911; ARMEB-NEXT:    bx lr
912;
913; THUMB1-LABEL: test7:
914; THUMB1:       @ %bb.0: @ %entry
915; THUMB1-NEXT:    ldrb r0, [r0]
916; THUMB1-NEXT:    ands r0, r1
917; THUMB1-NEXT:    uxtb r1, r2
918; THUMB1-NEXT:    subs r1, r0, r1
919; THUMB1-NEXT:    rsbs r0, r1, #0
920; THUMB1-NEXT:    adcs r0, r1
921; THUMB1-NEXT:    bx lr
922;
923; THUMB2-LABEL: test7:
924; THUMB2:       @ %bb.0: @ %entry
925; THUMB2-NEXT:    ldrb r0, [r0]
926; THUMB2-NEXT:    ands r0, r1
927; THUMB2-NEXT:    uxtb r1, r2
928; THUMB2-NEXT:    subs r0, r0, r1
929; THUMB2-NEXT:    clz r0, r0
930; THUMB2-NEXT:    lsrs r0, r0, #5
931; THUMB2-NEXT:    bx lr
932entry:
933  %0 = load i16, i16* %x, align 4
934  %1 = and i16 %0, %y
935  %2 = trunc i16 %1 to i8
936  %3 = icmp eq i8 %2, %z
937  ret i1 %3
938}
939
940define arm_aapcscc void @test8(i32* nocapture %p) {
941; ARM-LABEL: test8:
942; ARM:       @ %bb.0: @ %entry
943; ARM-NEXT:    ldrb r1, [r0]
944; ARM-NEXT:    eor r1, r1, #255
945; ARM-NEXT:    str r1, [r0]
946; ARM-NEXT:    bx lr
947;
948; ARMEB-LABEL: test8:
949; ARMEB:       @ %bb.0: @ %entry
950; ARMEB-NEXT:    ldrb r1, [r0, #3]
951; ARMEB-NEXT:    eor r1, r1, #255
952; ARMEB-NEXT:    str r1, [r0]
953; ARMEB-NEXT:    bx lr
954;
955; THUMB1-LABEL: test8:
956; THUMB1:       @ %bb.0: @ %entry
957; THUMB1-NEXT:    ldrb r1, [r0]
958; THUMB1-NEXT:    movs r2, #255
959; THUMB1-NEXT:    eors r2, r1
960; THUMB1-NEXT:    str r2, [r0]
961; THUMB1-NEXT:    bx lr
962;
963; THUMB2-LABEL: test8:
964; THUMB2:       @ %bb.0: @ %entry
965; THUMB2-NEXT:    ldrb r1, [r0]
966; THUMB2-NEXT:    eor r1, r1, #255
967; THUMB2-NEXT:    str r1, [r0]
968; THUMB2-NEXT:    bx lr
969entry:
970  %0 = load i32, i32* %p, align 4
971  %neg = and i32 %0, 255
972  %and = xor i32 %neg, 255
973  store i32 %and, i32* %p, align 4
974  ret void
975}
976
977define arm_aapcscc void @test9(i32* nocapture %p) {
978; ARM-LABEL: test9:
979; ARM:       @ %bb.0: @ %entry
980; ARM-NEXT:    ldrb r1, [r0]
981; ARM-NEXT:    eor r1, r1, #255
982; ARM-NEXT:    str r1, [r0]
983; ARM-NEXT:    bx lr
984;
985; ARMEB-LABEL: test9:
986; ARMEB:       @ %bb.0: @ %entry
987; ARMEB-NEXT:    ldrb r1, [r0, #3]
988; ARMEB-NEXT:    eor r1, r1, #255
989; ARMEB-NEXT:    str r1, [r0]
990; ARMEB-NEXT:    bx lr
991;
992; THUMB1-LABEL: test9:
993; THUMB1:       @ %bb.0: @ %entry
994; THUMB1-NEXT:    ldrb r1, [r0]
995; THUMB1-NEXT:    movs r2, #255
996; THUMB1-NEXT:    eors r2, r1
997; THUMB1-NEXT:    str r2, [r0]
998; THUMB1-NEXT:    bx lr
999;
1000; THUMB2-LABEL: test9:
1001; THUMB2:       @ %bb.0: @ %entry
1002; THUMB2-NEXT:    ldrb r1, [r0]
1003; THUMB2-NEXT:    eor r1, r1, #255
1004; THUMB2-NEXT:    str r1, [r0]
1005; THUMB2-NEXT:    bx lr
1006entry:
1007  %0 = load i32, i32* %p, align 4
1008  %neg = xor i32 %0, -1
1009  %and = and i32 %neg, 255
1010  store i32 %and, i32* %p, align 4
1011  ret void
1012}
1013
1014define arm_aapcscc void @test10(i32* nocapture %p) {
1015; ARM-LABEL: test10:
1016; ARM:       @ %bb.0: @ %entry
1017; ARM-NEXT:    ldrb r1, [r0]
1018; ARM-NEXT:    eor r1, r1, #255
1019; ARM-NEXT:    str r1, [r0]
1020; ARM-NEXT:    bx lr
1021;
1022; ARMEB-LABEL: test10:
1023; ARMEB:       @ %bb.0: @ %entry
1024; ARMEB-NEXT:    ldrb r1, [r0, #3]
1025; ARMEB-NEXT:    eor r1, r1, #255
1026; ARMEB-NEXT:    str r1, [r0]
1027; ARMEB-NEXT:    bx lr
1028;
1029; THUMB1-LABEL: test10:
1030; THUMB1:       @ %bb.0: @ %entry
1031; THUMB1-NEXT:    ldrb r1, [r0]
1032; THUMB1-NEXT:    movs r2, #255
1033; THUMB1-NEXT:    eors r2, r1
1034; THUMB1-NEXT:    str r2, [r0]
1035; THUMB1-NEXT:    bx lr
1036;
1037; THUMB2-LABEL: test10:
1038; THUMB2:       @ %bb.0: @ %entry
1039; THUMB2-NEXT:    ldrb r1, [r0]
1040; THUMB2-NEXT:    eor r1, r1, #255
1041; THUMB2-NEXT:    str r1, [r0]
1042; THUMB2-NEXT:    bx lr
1043entry:
1044  %0 = load i32, i32* %p, align 4
1045  %neg = and i32 %0, 255
1046  %and = xor i32 %neg, 255
1047  store i32 %and, i32* %p, align 4
1048  ret void
1049}
1050
1051define arm_aapcscc i32 @test11(i32* nocapture %p) {
1052; ARM-LABEL: test11:
1053; ARM:       @ %bb.0:
1054; ARM-NEXT:    ldrb r0, [r0, #1]
1055; ARM-NEXT:    lsl r0, r0, #8
1056; ARM-NEXT:    bx lr
1057;
1058; ARMEB-LABEL: test11:
1059; ARMEB:       @ %bb.0:
1060; ARMEB-NEXT:    ldrb r0, [r0, #2]
1061; ARMEB-NEXT:    lsl r0, r0, #8
1062; ARMEB-NEXT:    bx lr
1063;
1064; THUMB1-LABEL: test11:
1065; THUMB1:       @ %bb.0:
1066; THUMB1-NEXT:    ldrb r0, [r0, #1]
1067; THUMB1-NEXT:    lsls r0, r0, #8
1068; THUMB1-NEXT:    bx lr
1069;
1070; THUMB2-LABEL: test11:
1071; THUMB2:       @ %bb.0:
1072; THUMB2-NEXT:    ldrb r0, [r0, #1]
1073; THUMB2-NEXT:    lsls r0, r0, #8
1074; THUMB2-NEXT:    bx lr
1075  %1 = load i32, i32* %p, align 4
1076  %and = and i32 %1, 65280
1077  ret i32 %and
1078}
1079
1080define arm_aapcscc i32 @test12(i32* nocapture %p) {
1081; ARM-LABEL: test12:
1082; ARM:       @ %bb.0:
1083; ARM-NEXT:    ldrb r0, [r0, #2]
1084; ARM-NEXT:    lsl r0, r0, #16
1085; ARM-NEXT:    bx lr
1086;
1087; ARMEB-LABEL: test12:
1088; ARMEB:       @ %bb.0:
1089; ARMEB-NEXT:    ldrb r0, [r0, #1]
1090; ARMEB-NEXT:    lsl r0, r0, #16
1091; ARMEB-NEXT:    bx lr
1092;
1093; THUMB1-LABEL: test12:
1094; THUMB1:       @ %bb.0:
1095; THUMB1-NEXT:    ldrb r0, [r0, #2]
1096; THUMB1-NEXT:    lsls r0, r0, #16
1097; THUMB1-NEXT:    bx lr
1098;
1099; THUMB2-LABEL: test12:
1100; THUMB2:       @ %bb.0:
1101; THUMB2-NEXT:    ldrb r0, [r0, #2]
1102; THUMB2-NEXT:    lsls r0, r0, #16
1103; THUMB2-NEXT:    bx lr
1104  %1 = load i32, i32* %p, align 4
1105  %and = and i32 %1, 16711680
1106  ret i32 %and
1107}
1108
1109define arm_aapcscc i32 @test13(i32* nocapture %p) {
1110; ARM-LABEL: test13:
1111; ARM:       @ %bb.0:
1112; ARM-NEXT:    ldrb r0, [r0, #3]
1113; ARM-NEXT:    lsl r0, r0, #24
1114; ARM-NEXT:    bx lr
1115;
1116; ARMEB-LABEL: test13:
1117; ARMEB:       @ %bb.0:
1118; ARMEB-NEXT:    ldrb r0, [r0]
1119; ARMEB-NEXT:    lsl r0, r0, #24
1120; ARMEB-NEXT:    bx lr
1121;
1122; THUMB1-LABEL: test13:
1123; THUMB1:       @ %bb.0:
1124; THUMB1-NEXT:    ldrb r0, [r0, #3]
1125; THUMB1-NEXT:    lsls r0, r0, #24
1126; THUMB1-NEXT:    bx lr
1127;
1128; THUMB2-LABEL: test13:
1129; THUMB2:       @ %bb.0:
1130; THUMB2-NEXT:    ldrb r0, [r0, #3]
1131; THUMB2-NEXT:    lsls r0, r0, #24
1132; THUMB2-NEXT:    bx lr
1133  %1 = load i32, i32* %p, align 4
1134  %and = and i32 %1, 4278190080
1135  ret i32 %and
1136}
1137
1138define arm_aapcscc i32 @test14(i32* nocapture %p) {
1139; ARM-LABEL: test14:
1140; ARM:       @ %bb.0:
1141; ARM-NEXT:    ldrh r0, [r0, #1]
1142; ARM-NEXT:    lsl r0, r0, #8
1143; ARM-NEXT:    bx lr
1144;
1145; ARMEB-LABEL: test14:
1146; ARMEB:       @ %bb.0:
1147; ARMEB-NEXT:    ldrh r0, [r0, #1]
1148; ARMEB-NEXT:    lsl r0, r0, #8
1149; ARMEB-NEXT:    bx lr
1150;
1151; THUMB1-LABEL: test14:
1152; THUMB1:       @ %bb.0:
1153; THUMB1-NEXT:    ldr r1, [r0]
1154; THUMB1-NEXT:    ldr r0, .LCPI26_0
1155; THUMB1-NEXT:    ands r0, r1
1156; THUMB1-NEXT:    bx lr
1157; THUMB1-NEXT:    .p2align 2
1158; THUMB1-NEXT:  @ %bb.1:
1159; THUMB1-NEXT:  .LCPI26_0:
1160; THUMB1-NEXT:    .long 16776960 @ 0xffff00
1161;
1162; THUMB2-LABEL: test14:
1163; THUMB2:       @ %bb.0:
1164; THUMB2-NEXT:    ldrh.w r0, [r0, #1]
1165; THUMB2-NEXT:    lsls r0, r0, #8
1166; THUMB2-NEXT:    bx lr
1167  %1 = load i32, i32* %p, align 4
1168  %and = and i32 %1, 16776960
1169  ret i32 %and
1170}
1171
1172define arm_aapcscc i32 @test15(i32* nocapture %p) {
1173; ARM-LABEL: test15:
1174; ARM:       @ %bb.0:
1175; ARM-NEXT:    ldrh r0, [r0, #2]
1176; ARM-NEXT:    lsl r0, r0, #16
1177; ARM-NEXT:    bx lr
1178;
1179; ARMEB-LABEL: test15:
1180; ARMEB:       @ %bb.0:
1181; ARMEB-NEXT:    ldrh r0, [r0]
1182; ARMEB-NEXT:    lsl r0, r0, #16
1183; ARMEB-NEXT:    bx lr
1184;
1185; THUMB1-LABEL: test15:
1186; THUMB1:       @ %bb.0:
1187; THUMB1-NEXT:    ldrh r0, [r0, #2]
1188; THUMB1-NEXT:    lsls r0, r0, #16
1189; THUMB1-NEXT:    bx lr
1190;
1191; THUMB2-LABEL: test15:
1192; THUMB2:       @ %bb.0:
1193; THUMB2-NEXT:    ldrh r0, [r0, #2]
1194; THUMB2-NEXT:    lsls r0, r0, #16
1195; THUMB2-NEXT:    bx lr
1196  %1 = load i32, i32* %p, align 4
1197  %and = and i32 %1, 4294901760
1198  ret i32 %and
1199}
1200
1201define arm_aapcscc i32 @test16(i64* nocapture %p) {
1202; ARM-LABEL: test16:
1203; ARM:       @ %bb.0:
1204; ARM-NEXT:    ldrb r0, [r0, #1]
1205; ARM-NEXT:    lsl r0, r0, #8
1206; ARM-NEXT:    bx lr
1207;
1208; ARMEB-LABEL: test16:
1209; ARMEB:       @ %bb.0:
1210; ARMEB-NEXT:    ldrb r0, [r0, #6]
1211; ARMEB-NEXT:    lsl r0, r0, #8
1212; ARMEB-NEXT:    bx lr
1213;
1214; THUMB1-LABEL: test16:
1215; THUMB1:       @ %bb.0:
1216; THUMB1-NEXT:    ldrb r0, [r0, #1]
1217; THUMB1-NEXT:    lsls r0, r0, #8
1218; THUMB1-NEXT:    bx lr
1219;
1220; THUMB2-LABEL: test16:
1221; THUMB2:       @ %bb.0:
1222; THUMB2-NEXT:    ldrb r0, [r0, #1]
1223; THUMB2-NEXT:    lsls r0, r0, #8
1224; THUMB2-NEXT:    bx lr
1225  %1 = load i64, i64* %p, align 8
1226  %and = and i64 %1, 65280
1227  %trunc = trunc i64 %and to i32
1228  ret i32 %trunc
1229}
1230
1231define arm_aapcscc i32 @test17(i64* nocapture %p) {
1232; ARM-LABEL: test17:
1233; ARM:       @ %bb.0:
1234; ARM-NEXT:    ldrb r0, [r0, #2]
1235; ARM-NEXT:    lsl r0, r0, #16
1236; ARM-NEXT:    bx lr
1237;
1238; ARMEB-LABEL: test17:
1239; ARMEB:       @ %bb.0:
1240; ARMEB-NEXT:    ldrb r0, [r0, #5]
1241; ARMEB-NEXT:    lsl r0, r0, #16
1242; ARMEB-NEXT:    bx lr
1243;
1244; THUMB1-LABEL: test17:
1245; THUMB1:       @ %bb.0:
1246; THUMB1-NEXT:    ldrb r0, [r0, #2]
1247; THUMB1-NEXT:    lsls r0, r0, #16
1248; THUMB1-NEXT:    bx lr
1249;
1250; THUMB2-LABEL: test17:
1251; THUMB2:       @ %bb.0:
1252; THUMB2-NEXT:    ldrb r0, [r0, #2]
1253; THUMB2-NEXT:    lsls r0, r0, #16
1254; THUMB2-NEXT:    bx lr
1255  %1 = load i64, i64* %p, align 8
1256  %and = and i64 %1, 16711680
1257  %trunc = trunc i64 %and to i32
1258  ret i32 %trunc
1259}
1260
1261define arm_aapcscc i32 @test18(i64* nocapture %p) {
1262; ARM-LABEL: test18:
1263; ARM:       @ %bb.0:
1264; ARM-NEXT:    ldrb r0, [r0, #3]
1265; ARM-NEXT:    lsl r0, r0, #24
1266; ARM-NEXT:    bx lr
1267;
1268; ARMEB-LABEL: test18:
1269; ARMEB:       @ %bb.0:
1270; ARMEB-NEXT:    ldrb r0, [r0, #4]
1271; ARMEB-NEXT:    lsl r0, r0, #24
1272; ARMEB-NEXT:    bx lr
1273;
1274; THUMB1-LABEL: test18:
1275; THUMB1:       @ %bb.0:
1276; THUMB1-NEXT:    ldrb r0, [r0, #3]
1277; THUMB1-NEXT:    lsls r0, r0, #24
1278; THUMB1-NEXT:    bx lr
1279;
1280; THUMB2-LABEL: test18:
1281; THUMB2:       @ %bb.0:
1282; THUMB2-NEXT:    ldrb r0, [r0, #3]
1283; THUMB2-NEXT:    lsls r0, r0, #24
1284; THUMB2-NEXT:    bx lr
1285  %1 = load i64, i64* %p, align 8
1286  %and = and i64 %1, 4278190080
1287  %trunc = trunc i64 %and to i32
1288  ret i32 %trunc
1289}
1290
1291define arm_aapcscc i64 @test19(i64* nocapture %p) {
1292; ARM-LABEL: test19:
1293; ARM:       @ %bb.0:
1294; ARM-NEXT:    ldrb r1, [r0, #4]
1295; ARM-NEXT:    mov r0, #0
1296; ARM-NEXT:    bx lr
1297;
1298; ARMEB-LABEL: test19:
1299; ARMEB:       @ %bb.0:
1300; ARMEB-NEXT:    ldrb r0, [r0, #3]
1301; ARMEB-NEXT:    mov r1, #0
1302; ARMEB-NEXT:    bx lr
1303;
1304; THUMB1-LABEL: test19:
1305; THUMB1:       @ %bb.0:
1306; THUMB1-NEXT:    ldrb r1, [r0, #4]
1307; THUMB1-NEXT:    movs r0, #0
1308; THUMB1-NEXT:    bx lr
1309;
1310; THUMB2-LABEL: test19:
1311; THUMB2:       @ %bb.0:
1312; THUMB2-NEXT:    ldrb r1, [r0, #4]
1313; THUMB2-NEXT:    movs r0, #0
1314; THUMB2-NEXT:    bx lr
1315  %1 = load i64, i64* %p, align 8
1316  %and = and i64 %1, 1095216660480
1317  ret i64 %and
1318}
1319
1320define arm_aapcscc i64 @test20(i64* nocapture %p) {
1321; ARM-LABEL: test20:
1322; ARM:       @ %bb.0:
1323; ARM-NEXT:    ldrb r0, [r0, #5]
1324; ARM-NEXT:    lsl r1, r0, #8
1325; ARM-NEXT:    mov r0, #0
1326; ARM-NEXT:    bx lr
1327;
1328; ARMEB-LABEL: test20:
1329; ARMEB:       @ %bb.0:
1330; ARMEB-NEXT:    ldrb r0, [r0, #2]
1331; ARMEB-NEXT:    mov r1, #0
1332; ARMEB-NEXT:    lsl r0, r0, #8
1333; ARMEB-NEXT:    bx lr
1334;
1335; THUMB1-LABEL: test20:
1336; THUMB1:       @ %bb.0:
1337; THUMB1-NEXT:    ldrb r0, [r0, #5]
1338; THUMB1-NEXT:    lsls r1, r0, #8
1339; THUMB1-NEXT:    movs r0, #0
1340; THUMB1-NEXT:    bx lr
1341;
1342; THUMB2-LABEL: test20:
1343; THUMB2:       @ %bb.0:
1344; THUMB2-NEXT:    ldrb r0, [r0, #5]
1345; THUMB2-NEXT:    lsls r1, r0, #8
1346; THUMB2-NEXT:    movs r0, #0
1347; THUMB2-NEXT:    bx lr
1348  %1 = load i64, i64* %p, align 8
1349  %and = and i64 %1, 280375465082880
1350  ret i64 %and
1351}
1352
1353define arm_aapcscc i64 @test21(i64* nocapture %p) {
1354; ARM-LABEL: test21:
1355; ARM:       @ %bb.0:
1356; ARM-NEXT:    ldrb r0, [r0, #6]
1357; ARM-NEXT:    lsl r1, r0, #16
1358; ARM-NEXT:    mov r0, #0
1359; ARM-NEXT:    bx lr
1360;
1361; ARMEB-LABEL: test21:
1362; ARMEB:       @ %bb.0:
1363; ARMEB-NEXT:    ldrb r0, [r0, #1]
1364; ARMEB-NEXT:    mov r1, #0
1365; ARMEB-NEXT:    lsl r0, r0, #16
1366; ARMEB-NEXT:    bx lr
1367;
1368; THUMB1-LABEL: test21:
1369; THUMB1:       @ %bb.0:
1370; THUMB1-NEXT:    ldrb r0, [r0, #6]
1371; THUMB1-NEXT:    lsls r1, r0, #16
1372; THUMB1-NEXT:    movs r0, #0
1373; THUMB1-NEXT:    bx lr
1374;
1375; THUMB2-LABEL: test21:
1376; THUMB2:       @ %bb.0:
1377; THUMB2-NEXT:    ldrb r0, [r0, #6]
1378; THUMB2-NEXT:    lsls r1, r0, #16
1379; THUMB2-NEXT:    movs r0, #0
1380; THUMB2-NEXT:    bx lr
1381  %1 = load i64, i64* %p, align 8
1382  %and = and i64 %1, 71776119061217280
1383  ret i64 %and
1384}
1385
1386define arm_aapcscc i64 @test22(i64* nocapture %p) {
1387; ARM-LABEL: test22:
1388; ARM:       @ %bb.0:
1389; ARM-NEXT:    ldrb r0, [r0, #7]
1390; ARM-NEXT:    lsl r1, r0, #24
1391; ARM-NEXT:    mov r0, #0
1392; ARM-NEXT:    bx lr
1393;
1394; ARMEB-LABEL: test22:
1395; ARMEB:       @ %bb.0:
1396; ARMEB-NEXT:    ldrb r0, [r0]
1397; ARMEB-NEXT:    mov r1, #0
1398; ARMEB-NEXT:    lsl r0, r0, #24
1399; ARMEB-NEXT:    bx lr
1400;
1401; THUMB1-LABEL: test22:
1402; THUMB1:       @ %bb.0:
1403; THUMB1-NEXT:    ldrb r0, [r0, #7]
1404; THUMB1-NEXT:    lsls r1, r0, #24
1405; THUMB1-NEXT:    movs r0, #0
1406; THUMB1-NEXT:    bx lr
1407;
1408; THUMB2-LABEL: test22:
1409; THUMB2:       @ %bb.0:
1410; THUMB2-NEXT:    ldrb r0, [r0, #7]
1411; THUMB2-NEXT:    lsls r1, r0, #24
1412; THUMB2-NEXT:    movs r0, #0
1413; THUMB2-NEXT:    bx lr
1414  %1 = load i64, i64* %p, align 8
1415  %and = and i64 %1, -72057594037927936
1416  ret i64 %and
1417}
1418
1419define arm_aapcscc i64 @test23(i64* nocapture %p) {
1420; ARM-LABEL: test23:
1421; ARM:       @ %bb.0:
1422; ARM-NEXT:    ldrh r1, [r0, #3]
1423; ARM-NEXT:    lsl r0, r1, #24
1424; ARM-NEXT:    lsr r1, r1, #8
1425; ARM-NEXT:    bx lr
1426;
1427; ARMEB-LABEL: test23:
1428; ARMEB:       @ %bb.0:
1429; ARMEB-NEXT:    ldrh r1, [r0, #3]
1430; ARMEB-NEXT:    lsr r0, r1, #8
1431; ARMEB-NEXT:    lsl r1, r1, #24
1432; ARMEB-NEXT:    bx lr
1433;
1434; THUMB1-LABEL: test23:
1435; THUMB1:       @ %bb.0:
1436; THUMB1-NEXT:    ldrb r1, [r0, #4]
1437; THUMB1-NEXT:    ldrb r0, [r0, #3]
1438; THUMB1-NEXT:    lsls r0, r0, #24
1439; THUMB1-NEXT:    bx lr
1440;
1441; THUMB2-LABEL: test23:
1442; THUMB2:       @ %bb.0:
1443; THUMB2-NEXT:    ldrh.w r1, [r0, #3]
1444; THUMB2-NEXT:    lsls r0, r1, #24
1445; THUMB2-NEXT:    lsrs r1, r1, #8
1446; THUMB2-NEXT:    bx lr
1447  %1 = load i64, i64* %p, align 8
1448  %and = and i64 %1, 1099494850560
1449  ret i64 %and
1450}
1451
1452define arm_aapcscc i64 @test24(i64* nocapture %p) {
1453; ARM-LABEL: test24:
1454; ARM:       @ %bb.0:
1455; ARM-NEXT:    ldrh r1, [r0, #4]
1456; ARM-NEXT:    mov r0, #0
1457; ARM-NEXT:    bx lr
1458;
1459; ARMEB-LABEL: test24:
1460; ARMEB:       @ %bb.0:
1461; ARMEB-NEXT:    ldrh r0, [r0, #2]
1462; ARMEB-NEXT:    mov r1, #0
1463; ARMEB-NEXT:    bx lr
1464;
1465; THUMB1-LABEL: test24:
1466; THUMB1:       @ %bb.0:
1467; THUMB1-NEXT:    ldrh r1, [r0, #4]
1468; THUMB1-NEXT:    movs r0, #0
1469; THUMB1-NEXT:    bx lr
1470;
1471; THUMB2-LABEL: test24:
1472; THUMB2:       @ %bb.0:
1473; THUMB2-NEXT:    ldrh r1, [r0, #4]
1474; THUMB2-NEXT:    movs r0, #0
1475; THUMB2-NEXT:    bx lr
1476  %1 = load i64, i64* %p, align 8
1477  %and = and i64 %1, 281470681743360
1478  ret i64 %and
1479}
1480
1481define arm_aapcscc i64 @test25(i64* nocapture %p) {
1482; ARM-LABEL: test25:
1483; ARM:       @ %bb.0:
1484; ARM-NEXT:    ldrh r0, [r0, #5]
1485; ARM-NEXT:    lsl r1, r0, #8
1486; ARM-NEXT:    mov r0, #0
1487; ARM-NEXT:    bx lr
1488;
1489; ARMEB-LABEL: test25:
1490; ARMEB:       @ %bb.0:
1491; ARMEB-NEXT:    ldrh r0, [r0, #1]
1492; ARMEB-NEXT:    mov r1, #0
1493; ARMEB-NEXT:    lsl r0, r0, #8
1494; ARMEB-NEXT:    bx lr
1495;
1496; THUMB1-LABEL: test25:
1497; THUMB1:       @ %bb.0:
1498; THUMB1-NEXT:    ldr r0, [r0, #4]
1499; THUMB1-NEXT:    ldr r1, .LCPI37_0
1500; THUMB1-NEXT:    ands r1, r0
1501; THUMB1-NEXT:    movs r0, #0
1502; THUMB1-NEXT:    bx lr
1503; THUMB1-NEXT:    .p2align 2
1504; THUMB1-NEXT:  @ %bb.1:
1505; THUMB1-NEXT:  .LCPI37_0:
1506; THUMB1-NEXT:    .long 16776960 @ 0xffff00
1507;
1508; THUMB2-LABEL: test25:
1509; THUMB2:       @ %bb.0:
1510; THUMB2-NEXT:    ldrh.w r0, [r0, #5]
1511; THUMB2-NEXT:    lsls r1, r0, #8
1512; THUMB2-NEXT:    movs r0, #0
1513; THUMB2-NEXT:    bx lr
1514  %1 = load i64, i64* %p, align 8
1515  %and = and i64 %1, 72056494526300160
1516  ret i64 %and
1517}
1518
1519define arm_aapcscc i64 @test26(i64* nocapture %p) {
1520; ARM-LABEL: test26:
1521; ARM:       @ %bb.0:
1522; ARM-NEXT:    ldrh r0, [r0, #6]
1523; ARM-NEXT:    lsl r1, r0, #16
1524; ARM-NEXT:    mov r0, #0
1525; ARM-NEXT:    bx lr
1526;
1527; ARMEB-LABEL: test26:
1528; ARMEB:       @ %bb.0:
1529; ARMEB-NEXT:    ldrh r0, [r0]
1530; ARMEB-NEXT:    mov r1, #0
1531; ARMEB-NEXT:    lsl r0, r0, #16
1532; ARMEB-NEXT:    bx lr
1533;
1534; THUMB1-LABEL: test26:
1535; THUMB1:       @ %bb.0:
1536; THUMB1-NEXT:    ldrh r0, [r0, #6]
1537; THUMB1-NEXT:    lsls r1, r0, #16
1538; THUMB1-NEXT:    movs r0, #0
1539; THUMB1-NEXT:    bx lr
1540;
1541; THUMB2-LABEL: test26:
1542; THUMB2:       @ %bb.0:
1543; THUMB2-NEXT:    ldrh r0, [r0, #6]
1544; THUMB2-NEXT:    lsls r1, r0, #16
1545; THUMB2-NEXT:    movs r0, #0
1546; THUMB2-NEXT:    bx lr
1547  %1 = load i64, i64* %p, align 8
1548  %and = and i64 %1, -281474976710656
1549  ret i64 %and
1550}
1551
1552define void @test27(i32* nocapture %ptr) {
1553; ARM-LABEL: test27:
1554; ARM:       @ %bb.0: @ %entry
1555; ARM-NEXT:    ldrb r1, [r0, #1]
1556; ARM-NEXT:    lsl r1, r1, #16
1557; ARM-NEXT:    str r1, [r0]
1558; ARM-NEXT:    bx lr
1559;
1560; ARMEB-LABEL: test27:
1561; ARMEB:       @ %bb.0: @ %entry
1562; ARMEB-NEXT:    ldrb r1, [r0, #2]
1563; ARMEB-NEXT:    lsl r1, r1, #16
1564; ARMEB-NEXT:    str r1, [r0]
1565; ARMEB-NEXT:    bx lr
1566;
1567; THUMB1-LABEL: test27:
1568; THUMB1:       @ %bb.0: @ %entry
1569; THUMB1-NEXT:    ldrb r1, [r0, #1]
1570; THUMB1-NEXT:    lsls r1, r1, #16
1571; THUMB1-NEXT:    str r1, [r0]
1572; THUMB1-NEXT:    bx lr
1573;
1574; THUMB2-LABEL: test27:
1575; THUMB2:       @ %bb.0: @ %entry
1576; THUMB2-NEXT:    ldrb r1, [r0, #1]
1577; THUMB2-NEXT:    lsls r1, r1, #16
1578; THUMB2-NEXT:    str r1, [r0]
1579; THUMB2-NEXT:    bx lr
1580entry:
1581  %0 = load i32, i32* %ptr, align 4
1582  %and = and i32 %0, 65280
1583  %shl = shl i32 %and, 8
1584  store i32 %shl, i32* %ptr, align 4
1585  ret void
1586}
1587