1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -verify-machineinstrs -mtriple=armv8.6a-arm-none-eabi -mattr=+neon,+bf16,+fullfp16 | FileCheck %s 3 4declare bfloat @llvm.arm.neon.vcvtbfp2bf(float) 5 6; Hard float ABI 7declare <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float>) 8 9define arm_aapcs_vfpcc <4 x bfloat> @test_vcvt_bf16_f32_hardfp(<4 x float> %a) { 10; CHECK-LABEL: test_vcvt_bf16_f32_hardfp: 11; CHECK: @ %bb.0: @ %entry 12; CHECK-NEXT: vcvt.bf16.f32 d0, q0 13; CHECK-NEXT: bx lr 14entry: 15 %vcvtfp2bf1.i.i = call <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float> %a) 16 ret <4 x bfloat> %vcvtfp2bf1.i.i 17} 18 19define arm_aapcs_vfpcc bfloat @test_vcvth_bf16_f32_hardfp(float %a) { 20; CHECK-LABEL: test_vcvth_bf16_f32_hardfp: 21; CHECK: @ %bb.0: @ %entry 22; CHECK-NEXT: vcvtb.bf16.f32 s0, s0 23; CHECK-NEXT: bx lr 24entry: 25 %vcvtbfp2bf.i = call bfloat @llvm.arm.neon.vcvtbfp2bf(float %a) 26 ret bfloat %vcvtbfp2bf.i 27} 28 29; Soft float ABI 30declare <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16(<4 x float>) 31 32define <2 x i32> @test_vcvt_bf16_f32_softfp(<4 x float> %a) { 33; CHECK-LABEL: test_vcvt_bf16_f32_softfp: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: vmov d17, r2, r3 36; CHECK-NEXT: vmov d16, r0, r1 37; CHECK-NEXT: vcvt.bf16.f32 d16, q8 38; CHECK-NEXT: vmov r0, r1, d16 39; CHECK-NEXT: bx lr 40entry: 41 %vcvtfp2bf1.i.i = call <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16(<4 x float> %a) 42 %.cast = bitcast <4 x i16> %vcvtfp2bf1.i.i to <2 x i32> 43 ret <2 x i32> %.cast 44} 45 46define bfloat @test_vcvth_bf16_f32_softfp(float %a) #1 { 47; CHECK-LABEL: test_vcvth_bf16_f32_softfp: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vmov s0, r0 50; CHECK-NEXT: vcvtb.bf16.f32 s0, s0 51; CHECK-NEXT: vmov r0, s0 52; CHECK-NEXT: bx lr 53entry: 54 %vcvtbfp2bf.i = call bfloat @llvm.arm.neon.vcvtbfp2bf(float %a) #3 55 ret bfloat %vcvtbfp2bf.i 56} 57