1; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s
2
3; CHECK:      eor [[T:r[0-9]+]], [[T]], [[T]], asr #31
4; CHECK-NEXT: mov [[C1:r[0-9]+]], #1
5; CHECK-NEXT: orr [[T]], [[C1]], [[T]], lsl #1
6; CHECK-NEXT: clz [[T]], [[T]]
7define i32 @cls(i32 %t) {
8  %cls.i = call i32 @llvm.arm.cls(i32 %t)
9  ret i32 %cls.i
10}
11
12; CHECK: cmp r1, #0
13; CHECK: mvnne [[ADJUSTEDLO:r[0-9]+]], r0
14; CHECK: clz [[CLZLO:r[0-9]+]], [[ADJUSTEDLO]]
15; CHECK: eor [[A:r[0-9]+]], r1, r1, asr #31
16; CHECK: mov r1, #1
17; CHECK: orr [[A]], r1, [[A]], lsl #1
18; CHECK: clz [[CLSHI:r[0-9]+]], [[A]]
19; CHECK: cmp [[CLSHI]], #31
20; CHECK: addeq r0, [[CLZLO]], #31
21define i32 @cls64(i64 %t) {
22  %cls.i = call i32 @llvm.arm.cls64(i64 %t)
23  ret i32 %cls.i
24}
25
26declare i32 @llvm.arm.cls(i32) nounwind
27declare i32 @llvm.arm.cls64(i64) nounwind
28