1; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
2; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
3
4define i1 @f1(i32 %a, i32 %b) {
5; CHECK-LABEL: f1:
6; CHECK: subs r0, r0, r1
7; CHECK: movwne r0, #1
8; CHECK-T2: subs    r0, r0, r1
9; CHECK-T2: it      ne
10; CHECK-T2: movne   r0, #1
11    %tmp = icmp ne i32 %a, %b
12    ret i1 %tmp
13}
14
15define i1 @f2(i32 %a, i32 %b) {
16; CHECK-LABEL: f2:
17; CHECK: sub     r0, r0, r1
18; CHECK: clz     r0, r0
19; CHECK: lsr     r0, r0, #5
20; CHECK-T2: subs    r0, r0, r1
21; CHECK-T2: clz     r0, r0
22; CHECK-T2: lsrs    r0, r0, #5
23    %tmp = icmp eq i32 %a, %b
24    ret i1 %tmp
25}
26
27define i1 @f6(i32 %a, i32 %b) {
28; CHECK-LABEL: f6:
29; CHECK: sub     r0, r0, r1, lsl #5
30; CHECK: clz     r0, r0
31; CHECK: lsr     r0, r0, #5
32; CHECK-T2: sub.w   r0, r0, r1, lsl #5
33; CHECK-T2: clz     r0, r0
34; CHECK-T2: lsrs    r0, r0, #5
35    %tmp = shl i32 %b, 5
36    %tmp1 = icmp eq i32 %a, %tmp
37    ret i1 %tmp1
38}
39
40define i1 @f7(i32 %a, i32 %b) {
41; CHECK-LABEL: f7:
42; CHECK: subs    r0, r0, r1, lsr #6
43; CHECK: movwne  r0, #1
44; CHECK-T2: subs.w   r0, r0, r1, lsr #6
45; CHECK-T2: it      ne
46; CHECK-T2: movne   r0, #1
47    %tmp = lshr i32 %b, 6
48    %tmp1 = icmp ne i32 %a, %tmp
49    ret i1 %tmp1
50}
51
52define i1 @f8(i32 %a, i32 %b) {
53; CHECK-LABEL: f8:
54; CHECK: sub     r0, r0, r1, asr #7
55; CHECK: clz     r0, r0
56; CHECK: lsr     r0, r0, #5
57; CHECK-T2: sub.w   r0, r0, r1, asr #7
58; CHECK-T2: clz     r0, r0
59; CHECK-T2: lsrs    r0, r0, #5
60    %tmp = ashr i32 %b, 7
61    %tmp1 = icmp eq i32 %a, %tmp
62    ret i1 %tmp1
63}
64
65define i1 @f9(i32 %a) {
66; CHECK-LABEL: f9:
67; CHECK: subs    r0, r0, r0, ror #8
68; CHECK: movwne  r0, #1
69; CHECK-T2: subs.w   r0, r0, r0, ror #8
70; CHECK-T2: it      ne
71; CHECK-T2: movne   r0, #1
72    %l8 = shl i32 %a, 24
73    %r8 = lshr i32 %a, 8
74    %tmp = or i32 %l8, %r8
75    %tmp1 = icmp ne i32 %a, %tmp
76    ret i1 %tmp1
77}
78
79; CHECK-LABEL: swap_cmp_shl
80; CHECK: mov r2, #0
81; CHECK: cmp r1, r0, lsl #11
82; CHECK: movwlt r2, #1
83; CHECK-T2: mov{{.*}} r2, #0
84; CHECK-T2: cmp.w r1, r0, lsl #11
85; CHECK-T2: movlt r2, #1
86define arm_aapcscc i32 @swap_cmp_shl(i32 %a, i32 %b) {
87entry:
88  %shift = shl i32 %a, 11
89  %cmp = icmp sgt i32 %shift, %b
90  %conv = zext i1 %cmp to i32
91  ret i32 %conv
92}
93
94; CHECK-LABEL: swap_cmp_lshr
95; CHECK: mov r2, #0
96; CHECK: cmp r1, r0, lsr #11
97; CHECK: movwhi r2, #1
98; CHECK-T2: mov{{.*}} r2, #0
99; CHECK-T2: cmp.w r1, r0, lsr #11
100; CHECK-T2: movhi r2, #1
101define arm_aapcscc i32 @swap_cmp_lshr(i32 %a, i32 %b) {
102entry:
103  %shift = lshr i32 %a, 11
104  %cmp = icmp ult i32 %shift, %b
105  %conv = zext i1 %cmp to i32
106  ret i32 %conv
107}
108
109; CHECK-LABEL: swap_cmp_ashr
110; CHECK: mov r2, #0
111; CHECK: cmp r1, r0, asr #11
112; CHECK: movwle r2, #1
113; CHECK-T2: mov{{.*}} r2, #0
114; CHECK-T2: cmp.w r1, r0, asr #11
115; CHECK-T2: movle r2, #1
116define arm_aapcscc i32 @swap_cmp_ashr(i32 %a, i32 %b) {
117entry:
118  %shift = ashr i32 %a, 11
119  %cmp = icmp sge i32 %shift, %b
120  %conv = zext i1 %cmp to i32
121  ret i32 %conv
122}
123
124; CHECK-LABEL: swap_cmp_rotr
125; CHECK: mov r2, #0
126; CHECK: cmp r1, r0, ror #11
127; CHECK: movwls r2, #1
128; CHECK-T2: mov{{.*}} r2, #0
129; CHECK-T2: cmp.w r1, r0, ror #11
130; CHECK-T2: movls r2, #1
131define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) {
132entry:
133  %lsr = lshr i32 %a, 11
134  %lsl = shl i32 %a, 21
135  %ror = or i32 %lsr, %lsl
136  %cmp = icmp uge i32 %ror, %b
137  %conv = zext i1 %cmp to i32
138  ret i32 %conv
139}
140