1; REQUIRES: asserts
2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
3; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
4
5; CHECK:       ********** MI Scheduling **********
6; We need second, post-ra scheduling to have STM instruction combined from single-stores
7; CHECK:       ********** MI Scheduling **********
8; CHECK:       schedule starting
9; CHECK:       STMIA_UPD
10; CHECK:       rdefs left
11; CHECK-NEXT:  Latency            : 2
12; CHECK:       Successors
13; CHECK:       Data
14; CHECK-SAME:  Latency=1
15
16define i32 @bar(i32 %v0, i32 %v1, i32 %v2, i32* %addr) {
17
18  %addr.1 = getelementptr i32, i32* %addr, i32 0
19  store i32 %v0, i32* %addr.1
20
21  %addr.2 = getelementptr i32, i32* %addr, i32 1
22  store i32 %v1, i32* %addr.2
23
24  %addr.3 = getelementptr i32, i32* %addr, i32 2
25  store i32 %v2, i32* %addr.3
26
27  %ptr_after = getelementptr i32, i32* %addr, i32 3
28  %val = ptrtoint i32* %ptr_after to i32
29
30  %rv1 = mul i32 %val, %v0
31  %rv2 = mul i32 %rv1, %v1
32  %rv3 = mul i32 %rv2, %v2
33
34  ret i32 %rv3
35}
36
37