1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -disable-post-ra -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
3; RUN: llc < %s -disable-post-ra -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
4
5; rdar://8984306
6define float @test1(float %x, float %y) nounwind {
7; SOFT-LABEL: test1:
8; SOFT:       @ %bb.0: @ %entry
9; SOFT-NEXT:    lsr r1, r1, #31
10; SOFT-NEXT:    bfi r0, r1, #31, #1
11; SOFT-NEXT:    bx lr
12;
13; HARD-LABEL: test1:
14; HARD:       @ %bb.0: @ %entry
15; HARD-NEXT:    vmov.f32 s2, s1
16; HARD-NEXT:    @ kill: def $s0 killed $s0 def $d0
17; HARD-NEXT:    vmov.i32 d16, #0x80000000
18; HARD-NEXT:    vbit d0, d1, d16
19; HARD-NEXT:    @ kill: def $s0 killed $s0 killed $d0
20; HARD-NEXT:    bx lr
21entry:
22
23  %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
24  ret float %0
25}
26
27define double @test2(double %x, double %y) nounwind {
28; SOFT-LABEL: test2:
29; SOFT:       @ %bb.0: @ %entry
30; SOFT-NEXT:    lsr r2, r3, #31
31; SOFT-NEXT:    bfi r1, r2, #31, #1
32; SOFT-NEXT:    bx lr
33;
34; HARD-LABEL: test2:
35; HARD:       @ %bb.0: @ %entry
36; HARD-NEXT:    vmov.i32 d16, #0x80000000
37; HARD-NEXT:    vshl.i64 d16, d16, #32
38; HARD-NEXT:    vbit d0, d1, d16
39; HARD-NEXT:    bx lr
40entry:
41
42  %0 = tail call double @copysign(double %x, double %y) nounwind readnone
43  ret double %0
44}
45
46define double @test3(double %x, double %y, double %z) nounwind {
47; SOFT-LABEL: test3:
48; SOFT:       @ %bb.0: @ %entry
49; SOFT-NEXT:    vmov d16, r2, r3
50; SOFT-NEXT:    vmov d17, r0, r1
51; SOFT-NEXT:    vmul.f64 d16, d17, d16
52; SOFT-NEXT:    vmov.i32 d17, #0x80000000
53; SOFT-NEXT:    vshl.i64 d17, d17, #32
54; SOFT-NEXT:    vldr d18, [sp]
55; SOFT-NEXT:    vbit d16, d18, d17
56; SOFT-NEXT:    vmov r0, r1, d16
57; SOFT-NEXT:    bx lr
58;
59; HARD-LABEL: test3:
60; HARD:       @ %bb.0: @ %entry
61; HARD-NEXT:    vmul.f64 d16, d0, d1
62; HARD-NEXT:    vmov.i32 d17, #0x80000000
63; HARD-NEXT:    vshl.i64 d17, d17, #32
64; HARD-NEXT:    vorr d0, d17, d17
65; HARD-NEXT:    vbsl d0, d2, d16
66; HARD-NEXT:    bx lr
67entry:
68  %0 = fmul double %x, %y
69  %1 = tail call double @copysign(double %0, double %z) nounwind readnone
70  ret double %1
71}
72
73; rdar://9287902
74define float @test4() nounwind {
75; SOFT-LABEL: test4:
76; SOFT:       @ %bb.0: @ %entry
77; SOFT-NEXT:    push {lr}
78; SOFT-NEXT:    bl _bar
79; SOFT-NEXT:    vmov d16, r0, r1
80; SOFT-NEXT:    vcvt.f32.f64 s0, d16
81; SOFT-NEXT:    vmov.i32 d17, #0x80000000
82; SOFT-NEXT:    vshr.u64 d16, d16, #32
83; SOFT-NEXT:    vmov.f32 d18, #5.000000e-01
84; SOFT-NEXT:    vbif d16, d18, d17
85; SOFT-NEXT:    vadd.f32 d0, d0, d16
86; SOFT-NEXT:    vmov r0, s0
87; SOFT-NEXT:    pop {lr}
88;
89; HARD-LABEL: test4:
90; HARD:       @ %bb.0: @ %entry
91; HARD-NEXT:    .save {r11, lr}
92; HARD-NEXT:    push {r11, lr}
93; HARD-NEXT:    bl bar
94; HARD-NEXT:    vmov d16, r0, r1
95; HARD-NEXT:    vcvt.f32.f64 s0, d16
96; HARD-NEXT:    vmov.i32 d17, #0x80000000
97; HARD-NEXT:    vshr.u64 d16, d16, #32
98; HARD-NEXT:    vmov.i32 d18, #0x3f000000
99; HARD-NEXT:    vorr d1, d17, d17
100; HARD-NEXT:    vbsl d1, d16, d18
101; HARD-NEXT:    vadd.f32 s0, s0, s2
102; HARD-NEXT:    pop {r11, pc}
103entry:
104  %0 = tail call double (...) @bar() nounwind
105  %1 = fptrunc double %0 to float
106  %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
107  %3 = fadd float %1, %2
108  ret float %3
109}
110
111declare double @bar(...)
112declare double @copysign(double, double) nounwind
113declare float @copysignf(float, float) nounwind
114